SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R08
Objective Specification
System description
Page 33 of 188
1.6.1.3
Switch-on sequence from power-off mode
Figure 19 shows the modules power-on sequence from the power-off mode, describing the following phases:
The external supply is still applied to the
VCC
inputs as it is assumed that the module has been previously
switched off by means of the AT+CPWROFF command: the
V_BCKP
output is internally enabled as proper
VCC
is present, the
RESET_N
of SARA-U2 series is set to high logic level due to internal pull-up to
V_BCKP
,
the
PWR_ON
is set to high logic level due to external pull-up connected to
V_BCKP
or
VCC
.
The
PWR_ON
input pin is set low for a valid time period, representing the start-up event.
All the generic digital pins of the modules are tri-stated until the switch-on of their supply source (
V_INT
):
any external signal connected to the generic digital pins must be tri-stated or set low at least until the
activation of the
V_INT
supply output to avoid latch-up of circuits and allow a proper boot of the module.
The
V_INT
generic digital interfaces supply output is enabled by the integrated power management unit.
The
RESET_N
line of SARA-G3 series rise suddenly to high logic level due to internal pull-up to
V_INT
.
The internal reset signal is held low by the integrated power management unit: the baseband processor core
and all the digital pins of the modules are held in reset state.
When the internal reset signal is released by the integrated power management unit, the processor core
starts to configure the digital pins of the modules to each default operational state.
The duration of this pins’ configuration phase differs within generic digital interfaces (3 s typical) and the
USB interface due to specific host / device enumeration timings (5 s typical, see section 1.9.3). The host
application processor should not send any AT command over the AT interfaces (USB, UART) of the modules
until the end of this interfaces’ configuration phase to allow a proper boot of the module.
After the interfaces’ configuration phase, the application can start sending AT commands, and the following
starting procedure is suggested to check the effective completion of the module internal boot sequence:
send AT and wait for the response with a 30 s timeout, iterate it 4 times without resetting or removing the
VCC
supply of the module, and then run the application.
VCC
V_BCKP
PWR_ON
SARA-U2 RESET_N
V_INT
SARA-G3 RESET_N
Internal Reset
System State
Digital Pins State
Internal Reset
→
Operational Operational
Tristate / Floating
OFF
ON
Internal Reset
0 ms
~35 ms
~3 s
Start of interface
configuration
Module interfaces
are configured
Start-up
event
Figure 19: SARA-G3 and SARA-U2 series power-on sequence from power-off mode
The Internal Reset signal is not available on a module pin, but the application can monitor the
V_INT
pin
to sense the start of the power-on sequence.
Before the switch-on of the generic digital interface supply source (
V_INT
) of the module, no voltage
driven by an external application should be applied to any generic digital interface of the modules.
