NORA-B1 series - System integration manual
UBX-20027617 - R02
Design-in
Page 31 of 58
C1-Public
Figure 10: NFC antenna design
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
′
=
1
(2
𝜋𝜋
× 13.56
𝑀𝑀𝑀𝑀𝑀𝑀
)
2
𝐿𝐿
𝑎𝑎𝑡𝑡𝑡𝑡
𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
′
=
1
2 ×
�𝐶𝐶
𝑝𝑝
+
𝐶𝐶
𝑖𝑖𝑡𝑡𝑡𝑡
+
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
�
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
=
2
(2
𝜋𝜋
× 13.56
𝑀𝑀𝑀𝑀𝑀𝑀
)
2
𝐿𝐿
𝑎𝑎𝑡𝑡𝑡𝑡
− 𝐶𝐶
𝑝𝑝
− 𝐶𝐶
𝑖𝑖𝑡𝑡𝑡𝑡
4.7.1.1
Battery protection
If the NFC antenna is exposed to a strong NFC field, current may flow in the opposite direction on the
supply because of parasitic diodes and ESD structures.
If the battery used does not tolerate a return current, protection must be placed between the battery
and the device to protect the battery. A series Schottky diode, or an “ideal diode” chip may be used,
such as the Maxim MAX4T.
4.8
General high-speed layout guidelines
These general design guidelines are considered as best practices and are valid for any bus present in
NORA-B1 series modules; designers should prioritize the layout of higher speed buses. Low frequency
signals are generally not critical for layout.
⚠
One exception is represented by high impedance traces (such as signals driven by weak pull
resistors) that may be affected by crosstalk. For those traces, a supplementary isolation of 4w
(four times the line width) from other buses is recommended.
4.8.1
General considerations for schematic design and PCB floor-planning
•
Verify which signal bus requires termination and add series resistor terminations to the
schematics.
•
Carefully consider the placement of the module with respect to antenna position and host
processor.
•
Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning.
•
Verify that the power supply design and power sequence are compliant with NORA-B1 series
module specification described in the NORA-B1 data sheet [1].
