NORA-B1 series - System integration manual
UBX-20027617 - R02
System description
Page 13 of 58
C1-Public
1.9.4
Analog pin options
Table 3 shows the supported connections of the analog functions.
☞
An analog pin may not be simultaneously connected to multiple functions.
Symbol
Analog function
Connects to
ADCP
ADC single-ended or differential positive input
Any analog pin or VDD
ADCN
ADC differential negative input
Any analog pin or VDD
VIN+
Comparator input
Any analog pin
VREF
Comparator single-ended mode reference
ladder input
Any analog pin, VDD, 1.2 V, 1.8V or 2.4V
VIN-
Comparator differential mode negative input
Any analog pin
Low-power comparator IN+
Any analog pin
LP_VIN-
Low-power comparator IN-
GPIO_16 or GPIO_18, 1/16 to 15/16 VDD in steps of 1/16 VDD
Table 3: Possible uses of the analog pin
1.10
Serial interfaces
1.10.1
Universal Asynchronous Receiver/Transmitter (UART)
NORA-B1 series modules support up to five UART ports for data communication. Four are available
through the application core. One is available through the network core.
The following UART signals are available:
•
Data lines (
RXD
as input,
TXD
as output)
•
Hardware flow control lines (
CTS
as input,
RTS
as output)
The UART can be used as either a 4-wire UART with hardware flow control or a 2-wire UART with only
TXD
and
RXD
.
Depending on the MCUboot bootloader configuration, one of the UART interfaces on the application
core can be used for software upgrades. See section 5 for more information. It is recommended that
this UART is connected to a header for software upgrades or made available for test points.
The I/O level of the UART follows the VDD voltage and it can thus be in the range of 1.7 V and 3.6 V. A
level shifter should be used if connecting NORA-B1 to a host with any other voltage on the UART
interface.
1.10.2
Serial Peripheral Interface (SPI)
NORA-B1 supports up to six SPI ports that can operate with a maximum serial clock frequency of
8 MHz in either controller (master) or peripheral (slave) mode. Five are available through the
application core. One is available through the network core. The SPI interfaces use the following
signals:
•
SCLK
•
MOSI
•
MISO
•
CS
•
DCX
(Data/Command signal) - This signal is optional but is sometimes used by the SPI slaves to
distinguish between SPI commands and data.
When using the SPI interface in controller mode, it is possible to use GPIOs as additional Chip Select
(CS) signals to allow the addressing of multiple slaves.
