NINA-B50 series - Hardware integration manual
UBX-22021116 - R02
Module integration
Page 17 of 57
C1-Public
An I2S interface always provides the LRCK and SCK clock signals in Main node, but some Main-node
devices
can’t
generate an MCK clock signal. NINA-B50 can supply a MCK
clock signal to both Main
and Sub nodes for external systems that
can’t
generate their own clock signal. The two data signals,
SDIN and SDOUT, allow for simultaneous bi-directional audio streaming. The interface supports 8, 16,
and 24-bit sample widths with up to 48 kHz sample rate.
2.5
Other Digital interfaces
2.5.1
Timer/ PWM Module (TPM)
NINA-B50 modules support three Pulse Width Modulation timers, TPM0, TPM1 and TPM2. TPM0 is a
2-channel 32-bit timer and TPM1 and TPM2 are 6-channel 32-bit timers.
The counter, compare, and capture registers are clocked by an asynchronous clock that can remain
enabled in low power modes.
2.5.2
Quadrature Decoder (QDEC)
The quadrature decoder (QDEC) is used to read quadrature encoded data from mechanical and optical
sensors in the form of digital waveforms. Quadrature encoded data is often used to indicate rotation
of a mechanical shaft in either a positive or negative direction.
The QDEC uses two inputs,
channel 0
(
PHASE_A)
and
channel 1 (PHASE_B)
, to control incremental
and decremental counting in the TPM counter. The QDEC supports two encoding modes: count and
direction encoding mode and phase encoding mode. See also
The TPM counter is clocked by the channel 0 and channel 1 input signals when quadrature decoder
mode is selected. Therefore, In quadrature decoder mode, channel 0 and channel 1 can only be used
in software compare mode. Other TPM channels can only be used in input capture or output compare
modes.
2.6
Analog interfaces
14 out of the 29 digital GPIOs can be multiplexed to analog functions. The following analog functions
are available:
•
1x 16-bit Analog to Digital Converter (ADC)
•
2x Low-power Comparator (LPCMP)
•
1x Voltage Reference (Vref)
☞
See also NINA-B50 data sheet
for detailed information on ADC, LPCMP and VREF.
2.7
Debug interfaces
2.7.1
SWD
NINA-B50 series modules provide one serial wire debug is a 2-pin electrical interface with a clock
(
SWDCLK
) and a single bi-directional data pin (
SWDIO
) to provide debug and test functionality.
Pin Name
SWD
Internal Pull up/Down
Type
Description
SWDCLK
I
Clock
Pull-down
SWDIO
I/O
Data
Pull-up
Table 4: SWD signals
