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LISA-U series - System Integration Manual
UBX-13001118 - R17
Advance information
System description
Page 42 of 190
When the internal reset signal is released by the integrated power management unit, the processor core
starts to configure the digital pins of the modules to each default operational state.
The duration of these pins’ configuration phase differs within generic digital interfaces (3 s typical) and USB
interface due to specific host / device enumeration timings (5 s typical, see the section 1.9.3.1). The host
application processor should not send any AT command over the AT interfaces (USB, UART) of the modules
until the end of these interfaces’ configuration phase to allow a proper boot of the module.
After the interfaces’ configuration phase, the application can start sending AT commands, and the following
starting procedure is suggested to check the effective completion of the module internal boot sequence:
send AT and wait for the response with a 30 s timeout, iterate it 4 times without resetting or removing the
VCC supply of the module, and then run the application.
VCC
V_BCKP
PWR_ON
V_INT
Internal Reset
System State
BB Pads State
Internal Reset
→
Operational Operational
Tristate / Floating Internal Reset
OFF
ON
Start-up
event
0 ms
~35 ms
~3 s
PWR_ON
can be set high
Start of interface
configuration
Generic digital interfaces
are configured
Figure 19: LISA-U series power-on sequence description
The Internal Reset signal is not available on a module pin, but the application can monitor the
V_INT
pin
to sense the start of the power-on sequence.
Any external signal connected to the UART interface, SPI/IPC interface, I
2
S interfaces and GPIOs must be
tri-stated when the module is in power-down mode, when the external reset is forced low and during the
module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and let a
proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated,
insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157)
between the two-circuit connections and set to high impedance during module power down mode, when
external reset is forced low and during power on sequence.