AMY-6M - Hardware Integration Manual
UBX-17021971 – R07
Design-in
Page 20 of 57
Figure 13: Connecting external serial I
2
C memory used by external host (see data sheet for exact pin orientation)
Note that the case shown on Figure 12 is different than the case when EEPROM is present but used by external
host / CPU as indicated on Figure 13. This is allowed but precaution is required to ensure that the GPS receiver
does not detect the EEPROM device, which would effectively configure the GPS receiver to be MASTER on the
bus causing collision with the external host.
To ensure that the EEPROM device (connected to the bus and used by the host) is not detected by the GPS
receiver it is important to set the EEPROM’s address to a value different than 0b10100000. This way EEPROM
remains free to be used for other purposes and the GPS receiver will assume the SLAVE mode.
Ensure that at the start up the host allows enough time for the receiver to communicate over the bus to
establish presence of the EEPROM. It is only when this interrogation is complete that the host can exercise
full control over the bus (MASTER mode).
The AMY-6M always interrogates external EEPROM at the start-up. The interrogation process is guaranteed
to complete within 250ms upon start up. This is the time the external host has to give to the ROM based
GPS receiver to complete the EEPROM interrogation.
The AMY-6M DDC interface supports serial communication with u-blox wireless modules. See the
specification of the applicable wireless module to confirm compatibility.
TX ready signal (data ready to be picked up) can be activated, for configuration see 2.4.1.3.
2.3.4
SPI
A Serial Peripheral Interface (SPI) is available. The SPI allows for the connection of external devices with a serial
interface, e.g. FLASH memories or A/D converters, or to interface to a host CPU. Background information about
the SPI interface is available in Appendix C.2.
2.3.4.1
Connecting SPI FLASH memory
SPI FLASH memory can be connected to the SPI interface to save AssistNow Offline data and/or receiver
configuration. It will automatically be recognized by firmware when connected to SS_N.
Figure 14 shows how external memory can be connected. Note that an external voltage is required to power the
FLASH (VDD_IO on the receiver is an input). Minimum SPI FLASH memory size is 1 Mbit.
