UBX-G7020 - Hardware Integration Manual
Design-in
GPS.G7-HW-10003
Objective Specification
Page 43 of 74
2.10
System Configuration
The UBX-G7020 applies the following configurations at startup:
1.
Communication Interface Configuration
2.
Low Level Configuration
3.
Functional Configuration
2.10.1
Communication Interface Configuration
The Communication Interface Configuration selects the interface for communication to the host CPU. The
selection is done according to the status of PIO10 (D_SEL pin). See section 2.2.3, Table 5.
2.10.2
Low Level Configuration
The low level configuration defines all the important system related settings and needs to be set initially in
production. It is mandatory for the UBX-G7020 that the Low Level Configuration is set correctly, otherwise it will
not work properly or may even not start up at all.
All the Low Level Configurations can be set in the eFuse inside the UBX-G7020 chip. If an SQI Flash is connected
to the UBX-G7020 a partial Low Level Configuration, i.e. all except the VDD_IO POR threshold can be saved
permanently in the SQI Flash. If no SQI Flash is connected some of the Low Level Configuration can be set by
configuration pins.
The parts of the Low Level Configuration held in the SQI Flash or set by Configuration Pins have higher priority
than the Low Level Configuration held within the UBX-G7020 eFuse.
If the clock/oscillator Low Level Configuration settings are incorrect, it is mandatory to start up in the Safe Boot
Mode. To do this, PIO12 the SAFEBOOT_N pin, must be low (see section 2.2.6) on startup. Usually this is
required with an SQI flash based design starting for the first time in production. That is, the eFuse settings are
not configured and the SQI flash has not yet been programmed with information about the clock/oscillator.
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