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3.3.3 Advanced Chipset Control
PhoenixBIOS Setup Utility
Main
Advanced
Security Power Boot Exit
Advanced Chipset Control
Item Specific Help
Crystal Beach Configuration
Enable:
SERR signal condition:
4GB PCI Hole Granularity:
Memory Branch Mode:
Branch 0 Rank Interleave:
Branch 0 Rank Sparing:
Branch 1 Rank Interleave:
Branch 1 Rank Sparing:
Enhanced x8 Detection:
Force ITK Config Clocking:
High Precision Event Timer:
Snoop filter:
[Disabled]
[Single bit]
[256MB]
[Interleave]
[4:1]
[Disabled]
[4:1]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
[Enabled]
F1
Help
↑↓
Select Item
-/+
Change Values
F9
Setup Defaults
Esc
Exit
←
→
Select Menu
Enter
Select
X
Sub-Menu
F10
Save and Exit
SERR signal condition
Select ECC error conditions that SERR# be asserted.
None /
Single bit
/ Multiple bit/ Both
4GB PCI Hole Granularity
This feature is used to select the granularity of PCI hole for PCI resource. If
MTRRs are not enough, we may use this option to reduce the MTRR
occupation.
256MB
/ 512MB / 1.0GB / 2.0GB
Memory Branch Mode
This option is used to select the type of memory operation mode.
Sequential /
Interleave
/ Mirror / Single Channel 0
Branch 0/1 Rank Sparing
This option is used to enable/disable Branch 0 rank/DIMM sparing feature.
Disabled
/ Enabled
Enhanced x8 Detection
This feature is used to enable/disable enhanced x8 DRAM UC error detection.
Содержание Tempest i5000XT S2696
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