TYAN S4882, Руководство пользователя

Страница: 44 / 60

http://www.TYAN.com
44
3.4.12 – Chipset Configuration Sub-Menu
Feature Option Description
Auto
Dram Bank Interleave Disable
Interleave memory blocks across dram
chip selects. BIOS will AUTO detect
capability on each Node.
Node memory Interleave Disable
AUTO
Interleave memory blocks across
processor nodes BIOS will AUTO detect
capability of Memory System.
Note: This cannot be enabled if ACPI
SRAT table is also enabled. Changing one
value will also toggle the other.
ECC Enable ECC check/correct mode. This is a Global
enable function for all blocks within CPU
core and North Bridge
Disable
Dram ECC Enable
Disable
If all memory in the system supports ECC,
enabling this will initial scrub dram and
enable system requests to dram to be
checked and/or corrected
ECC Scrub Redirection Enable
Disable
Enable ECC Scrubber to correct errors
detected in Dram during normal CPU
requests
4-bit ECC Enable
Disable
Enable 4-bit ECC mode on Nodes with
ECC capable dims.
DCACHE ECC Scrub CTL Disable
40ns/80ns/
160ns/320n
s/640ns/1.2
8us/2.56us
Set the rate of background scrubbing for
DCACHE lines
L2 ECC Scrub CTL Disable
40ns/80ns/
160ns/320n
s/640ns/1.2
8us/2.56us
Set the rate of background scrubbing for
L2 cache lines
Dram ECC Scrub CTL Disable
1.31ms
/2.62ms/5.2
4ms/10.49
ms/20.97m
s/42ms/84
ms
Set the rate of BACKGROUND scrubbing
for Dram.
Speculative TLB Reload Enable
Disable
Enable / Disable Speculative TLB Reload