TYAN S4880, Руководство пользователя

Страница: 42 / 60

http://www.TYAN.com
42
3.4.11 – 4GB Memory Hole Adjust
Feature Option Description
4GB Memory Hole Adjust Auto
Manual
Auto – Adjust the memory hole size
automatically according to the
memory space used by PCI devices
Manual
– Memory hole size is
determined manually
3.4.12 – Chipset Configuration Sub-Menu
Feature Option Description
Auto
Dram Bank Interleave Disable
Interleave memory blocks across
dram chip selects. BIOS will AUTO
detect capability on each Node.
ECC Enable ECC check/correct mode. This is a
Global enable function for all blocks
within CPU core and North Bridge
Disable
Dram ECC Enable
Disable
If all memory in the system supports
ECC, enabling this will initial scrub
dram and enable system requests to
dram to be checked and/or corrected
ECC Scrub Redirection Enable Enable ECC Scrubber to correct
errors detected in Dram during normal
CPU requests
Disable
4-bit ECC Enable
Disable Enable 4-bit ECC mode on Nodes
with ECC capable dims.
DCACHE ECC Scrub CTL Disable
40ns/80ns/160ns
/320ns/640ns/1.
28us/2.56us
Set the rate of background scrubbing
for DCACHE lines
L2 ECC Scrub CTL Disable
40ns/80ns/160ns
/320ns/640ns/1.
28us/2.56us
Set the rate of background scrubbing
for L2 cache lines
Dram ECC Scrub CTL Disable
1.31ms
/2.62ms/5.24ms/
10.49ms/20.97m
s/42ms/84ms
Set the rate of BACKGROUND
scrubbing for Dram.
Speculative TLB Reload Enable
Disable
Enable / Disable Speculative TLB
Reload