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64
4.3 BIOS Post Code
Code
Beeps / Description
Code
Beeps / Description
02h
Verify Real Mode
32h
Test CPU bus-clock
frequency
03h
Disable Non-Maskable
Interrupt (NMI)
33h Initialize
Phoenix
Dispatch
Manager
04h
Get CPU type
36h
Warm start shut down
06h
Initialize system hardware
38h
Shadow system BIOS ROM
08h
Initialize chipset with initial
POST values
3Ah
Autosize cache
09h
Set IN POST flag
3Ch
Advanced configuration of
chipset registers
0Ah
Initialize CPU registers
3Dh
Load alternate registers with
CMOS values
0Bh
Enable CPU cache
42h
Initialize interrupt vectors
0Ch
Initialize caches to initial
POST values
45h POST
device
initialization
0Eh
Initialize I/O component
46h
2-1-2-3. Check ROM
copyright notice
0Fh
Initialize the local bus IDE
48h
Check video configuration
against CMOS
10h Initialize
Power
Management
49h
Initialize PCI bus and
devices
11h
Load alternate registers with
initial POST values
4Ah
Initialize all video adapters
in system
12h
Restore CPU control word
during warm boot
4Bh
QuietBoot start (optional)
13h
Initialize PCI Bus Mastering
devices
4Ch
Shadow video BIOS ROM
14h
Initialize keyboard controller
4Eh
Display BIOS copyright
notice
16h
1-2-2-3. BIOS ROM
checksum
50h
Display CPU type and
speed
17h Initialize
cache
before
memory autosize
51h Initialize
EISA
board
18h
8254 timer initialization
52h
Test keyboard
1Ah 8237
DMA
controller
initialization
54h
Set key click if enabled
1Ch Reset
Programmable
Interrupt Controller
58h
2-2-3-1. Test for
unexpected interrupts
20h
1-3-1-1. Test DRAM refresh
59h
Initialize POST display
service
22h
1-3-1-3. Test 8742 KBD
Controller
5Ah
Display prompt "Press F2 to
enter SETUP"
24h
Set ES segment register to
4 GB
5Bh
Disable CPU cache
26h
Enable A20 line
5Ch
Test RAM between 512 and
640 KB
28h
Autosize DRAM
60h
Test extended memory
29h Initialize
POST
Memory
Manager
62h
Test extended memory
address lines
2Ah
Clear 512 KB base RAM
64h
Jump to UserPatch1
2Ch
1-3-4-1. RAM failure on
address
66h
Configure advanced cache
registers
Содержание S2892
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