TrueTime VME-SG2 560-5608, Руководство пользователя

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5
5
6
6
0
0
-
-
5
5
6
6
0
0
0
0
.
.
m
m
a
a
n
n
.
.
d
d
o
o
c
c
2
2
-
-
1
1
6
6
Rev. F
The following table lists the offset from the VME-SG-GPS base address where the
Control and Vector registers for each interrupt source is located.
BIM CONTROL REGISTERS
There is one control register for each interrupt source. Each 8-bit control registers is
divided into several fields. The following is a description of each bits functions:
bits: 0 - L0 (IRQ Interrupt Level bit 0)
1 - L1 ( " " " bit 1)
2 - L2 ( " " " bit 2)
3 - IRAC (Interrupt Auto Clear)
4 - IRE (Interrupt Enable)
5 - X/IN (External/Internal)
6 - FAC (Flag Auto Clear)
7 - Flag
L0, L1, L2 - Bits 0, 1 and 2 determine the interrupt response level. The following table
illustrates the possible settings:
IRAC (Interrupt Auto-Clear) - Set bit 3 to clear the Interrupt Enable bit (below) during an
interrupt acknowledge cycle responding to this request. To enable the interrupt for
further interrupts the IRE bit must be set again by writing to the control register.
IRE (Interrupt Enable) - Set bit 4 to enable the interrupt associated with the control
register.
Register Source Offset
INT0 Control External Event 0000
INT1 Control Rate Generator 0002
INT2 Control Coincidence Compare #1 Pulse 0004
INT3 Control Coincidence Compare #2 Pulse 0006
INT0 Vector External Event 0008
INT1 Vector Rate Generator 000A
INT2 Vector Coincidence Compare #1 Pulse 000C
INT3 Vector Coincidence Compare #2 Pulse 000E
L2 L1 L0 IRQ LEVEL
0 0 0 Disabled
0 0 1 IRQ1
0 1 0 IRQ2
0 1 1 IRQ3
1 0 0 IRQ4
1 0 1 IRQ5
1 1 0 IRQ6
1 1 1 IRQ7
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