
4DWAVE-DX
TECHNICAL REFERENCE MANUAL
Document
Rev 1.1
Trident Microsystems, Inc.
19
4.1.2.4
Legacy Control (Offset = 46h)
Bits
POR
Read/Write
Description
[7:3]
00000b
R/W
Reserved
[2]
0
R/W
Audio Engine Reset
0 = Normal
1 = Reset Audio Registers & Wave Engine State Machines
When this bit is ‘1’, the audio block (including wavetable and legacy audio) will be
reset. It must be set to ‘0’, to exit reset.
[1]
0
R/W
Sub-System Vendor ID Write Enable
0 = Sub-System Vendor ID is Read Only
1 = Sub-System Vendor ID is Read/Write
[0]
0
R
Reserved
4.1.3
Power Management Configuration
4.1.3.1
Capabilities ID (Offset = 48h)
Bits
POR
Read/Write
Description
[7:0]
01h
R
Identifies the capability as being the PCI Power Management Registers.
4.1.3.2
Next Item Pointer (Offset = 49h)
Bits
POR
Read/Write
Description
[7:0]
00h
R
By being 00h, indicates the end of the linked-list of extended capabilities.
4.1.3.3
Power Management Capabilities (Offset = 4Ah)
Bits
POR
Read/Write
Description
[15:11]
00000b
R
PME Support – The 4DWAVE-DX does not support PME# generation.
[10]
1
R
D2 Support – The 4DWAVE-DX supports D2 power state.
[9]
1
R
D1 Support – The 4DWAVE-DX supports D1 power state.
[8:6]
000b
R
Reserved
[5]
0
R
Device Specific Initialization – The 4DWAVE-DX does not require any device
specific initialization.
[4]
0
R
Auxiliary Power Source – The 4DWAVE-DX does not support separate internal
power support. (Or PME# generation.)
[3]
0
R
PME Clock - The 4DWAVE-DX does not support PME# generation and, therefore,
does not need the PCI clock to generate a PME#.
[2:0]
001b
R
Version – The 4DWAVE-DX support Revision 1.0 of the PCI Power Management
Interface specification.
Содержание 4DWAVE-DX
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