4DWAVE-DX
TECHNICAL REFERENCE MANUAL
Document
Rev 1.1
Trident Microsystems, Inc.
i
Trident 4DWAVE-DX
Technical Reference Manual
Страница 1: ...4DWAVE DX TECHNICAL REFERENCE MANUAL Document Rev 1 1 Trident Microsystems Inc i Trident 4DWAVE DX Technical Reference Manual ...
Страница 2: ...RRANTY MAY LAST OR THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES SO SUCH LIMITATIONS OR EXCLUSIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM JURISDICTION TO JURISDICTION Trident Microsystems Inc assumes no responsibility for the use of any circuit other than circuits embodied in a Trident Microsystems ...
Страница 3: ...3 1 2 12 Package and Ordering 3 1 3 REFERENCE DOCUMENTS 3 2 SYSTEM AND ARCHITECTURE OVERVIEW 4 2 1 PCI INTERFACE 5 2 2 LEGACY 5 2 3 VOICE BUFFER STREAM BUFFER 5 2 4 ADDRESS ENGINE 5 2 5 ENVELOPE ENGINE 5 2 6 MIXER 5 2 7 RECORDING ENGINE 6 2 8 AC 97 INTERFACE 6 3 PACKAGE AND PIN ASSIGNMENTS 7 3 1 PIN ASSIGNMENT TABLE AND SIGNAL DESCRIPTION 7 3 1 1 PCI Interface 8 3 1 2 AC 97 Interface 9 3 1 3 MIDI ...
Страница 4: ... 4 1 2 4 Legacy Control Offset 46h 19 4 1 3 Power Management Configuration 19 4 1 3 1 Capabilities ID Offset 48h 19 4 1 3 2 Next Item Pointer Offset 49h 19 4 1 3 3 Power Management Capabilities Offset 4Ah 19 4 1 3 4 Power Management Control Status Offset 4Ch 20 4 1 4 Interrupt Snooping Configuration 20 4 1 4 1 Interrupt Snooping Control Offset 50h 20 4 2 WAVE ENGINE AND CONTROL REGISTERS 21 4 2 1 ...
Страница 5: ...RS 31 6 1 1 Core 3 3V Only 31 6 1 2 I O 5V Signaling Environment 31 6 1 3 I O 3 3V Signaling Environment 31 6 2 AC PARAMETERS 32 6 2 1 Clocks 32 6 2 1 1 PCI Clock 32 6 2 2 PCI Signals 33 6 2 3 Resets 34 6 2 3 1 PCI Reset 34 6 2 3 AC 97 Reset Cold and Warm 34 6 2 4 AC 97 Signals 35 7 REFERENCE SCHEMATIC 36 8 4DWAVE DX REFERENCE BOARD BILL OF MATERIALS REVISED APRIL 23 1998 41 ...
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Страница 7: ...DX utilizes a Digital Enhanced Game Port when coupled with a DirectInput driver can save up to 12 of the CPU overhead nominally required by a conventional analog game port The 4DWAVE DX employs a high precision 26 bit digital mixer providing an accurate 20 bit output and higher than 90dB signal to noise ratio when used with a high quality AC 97 codec The 4DWAVE DX is designed with aggressive power...
Страница 8: ...bled or standard non DDMA PCI chipsets VirtualFM enhances audio experience through real time FM to wavetable conversion MPU 401 compatible UART for external or internal synthesis VirtualGS provides General MIDI GS command interpretation for wavetable effect synthesis 1 2 4 High Quality Audio and AC 97 Support CD quality audio with better or equal to 90dB signal to noise ratio using an external hig...
Страница 9: ...GS compliant sample Library 1 2 9 Power Management Desktop ACPI PPMI Compatible Software Controls AC 97 Codec Power States 1 2 10 Testability NAND Tree test mode Tri state all I Os test mode Loop back modes for Diagnostics All Mixer Channels can be captured 1 2 11 Process Advanced 0 35um process Low power 3 3V 5V safe operation 1 2 12 Package and Ordering 100 LQFP 14mm x 14mm x 1 4mm Ordering Part...
Страница 10: ...le a single driver set to support current and future generation devices This approach allows a stable maintainable code base The hardware software combinations provide the following acceleration and functions DirectSound acceleration 64 voice Wavetable synthesis Chorus effects Reverb effects FM Synthesis via VirtualFM technology General MIDI GS command interpreter via VirtualGM VirtualGS technolog...
Страница 11: ...undled DirectInput driver the Digitally Enhanced Game Port allows a dramatic reduction in both bus traffic and CPU utilization by removing the requirement of I O polling for the joystick position This can save up to 12 of CPU overhead this substantially enhances game performance and the gaming experience The MIDI port is supported with an MPU 401 compatible UART This port can also be used in an em...
Страница 12: ...be recorded in 16 bit stereo format This requires 4 bytes per sample or 192Kbytes for 1 second of record data The recording channel also supports independent down sampling and format conversion By down sampling the bus bandwidth and memory space can be reduced For instance voice function using 8 bit mono samples at 8KHz uses only 8K bytes per second 2 8 AC 97 Interface The AC 97 interface supports...
Страница 13: ...s are used for pin characteristics in the Type column in Sections 3 1 1 to 3 1 6 I Input O Output T Tri state PWR Power GND Ground PU Internal Pull Up The I O Buffer columns in Section 3 1 1 to 3 1 6 indicate the various I O buffer cells used in the 4DWAVE DX Table 3 1 shows the detailed I O buffer characteristics for each I O buffer type used Table 3 1 Detailed I O Buffer Characteristics I O Cell...
Страница 14: ...ive low to indicate it is ready to complete the current data phase 10 IRDY T I O BDT10_5S IRDY Initiator Ready is driven by the current master active low to indicate it is ready to complete the current data phase 14 STOP T I O BDT10_5S STOP Stop is driven by the current target to indicate that it desires to stop the current transaction 12 DEVSEL T I O BDT10_5S DEVSEL Device Select is driven active...
Страница 15: ...serial time division multiplexed AC 97 input data stream Note AC0 is used to differentiate with future secondary codecs such as AC1 AC2 etc in multiple AC 97 support 48 AC_RESET T O BDT6U_5S AC_RESET AC 97 Reset is the active low master reset signal This signal is controlled by the PCI RST signal and the internal Power Management register 3 1 3 MIDI Game Port Pin Number s Signal Name Type I O Buff...
Страница 16: ...I O TBD PME Power Management Event is an active low signal that informs the system core logic that an event has occurred that requires a modification to the power management state of the system This pin is intended for Notebook and motherboard design as PME is not available on PCI slot 42 ROM_DATA I O TBD Serial ROM Data signal This pin should be connected to the data pin of a 2 pin serial EEPROM ...
Страница 17: ... 61 62 63 64 65 66 67 68 69 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VCC AD20 VCC_5V AD19 AD18 AD17 AD16 C BE2 IRDY FRAME PERR TRDY DEVSEL VSS STOP SERR C BE1 PAR AD12 VCC AD15 AD14 AD13 AD11 VSS VCC AD10 AD8 VSS AD5 AD9 C BE0 AD7 AD6 AD4 AD2 AD1 ROM_DATA AD3 ROM_CLK I2S_SDATA VCC AD0 I2S_LRCLK VSS I2S_SCLK AC1_SDATA_IN AC_RESET_N AC_SYNC VSS AC0_SDATA_IN VCC AC_...
Страница 18: ...ICAL REFERENCE MANUAL 12 Trident Microsystems Inc 3 2 Physical Dimensions mm 0 50 TYP 14 typ 16 typ 0 6 0 0 15 1 60 max 0 05 0 15 0 7 100 LQFP 76 75 51 50 26 25 100 1 0 20 0 07 0 03 12 00 typ 12 00 typ 14 typ 16 typ 1 00 ref 1 40 0 05 ...
Страница 19: ...s defines the power management capabilities of 4DWAVE DX Table 4 1 4DWAVE DX PCI Configuration Register Space Offset Hex Byte 3 Byte 2 Byte 1 Byte 0 00h Device ID Read Only 2000h Vendor ID Read Only 1023h 04h Status Command 08h Class Code Read Only 040100h Revision ID Read Only 00h 0Ch BIST Read Only 0000h Header Type Read Only 00h Latency Timer Cache Line Size Read Only 0000h 10h Audio IO Base Ad...
Страница 20: ... The 4DWAVE DX does not support this feature This bit is hard wired to a 0 6 0 R W Parity Enable 0 Ignores parity errors 1 Report parity errors 5 0 R VGA palette snoop The 4DWAVE DX does not support this feature This bit is hard wired to a 0 4 0 R Enable the Memory Write and Invalidate command The 4DWAVE DX does not support this feature This bit is hard wired to a 0 3 0 R Enable the device to moni...
Страница 21: ... DEVSEL Timing The device supports Medium DEVSEL timing 8 0 R W 1 to Clear Data Parity Error Detected This bit is set by the Master device when 1 it detects a data parity error 2 it is the current Master and 3 when the Command bit 6 is enabled to report parity errors 7 0 R Capable of Fast Back to Back cycles The 4DWAVE DX does not support this feature This bit is hard wired to a 0 6 0 R User Defin...
Страница 22: ... this feature These bits are hardwired to a 00h 4 1 1 11 I O Base Address Offset 10h Bits POR Read Write Description 31 8 000000h R W I O Base Address 31 8 Specifies the MS 24 bits of the Audio I O base address 7 2 000000b R I O Base Address 7 2 Forces alignment to a 256 byte block 1 0 R Reserved 0 1 R I O Base identifier 4 1 1 12 Memory Base Address Offset 14h Bits POR Read Write Description 31 1...
Страница 23: ...R Read Write Description 7 0 01h R Interrupt Pin This is used to tell what pin the device uses The 4DWAVE DX uses the INTA pin 4 1 1 18 Minimum Grant Offset 3Eh Bits POR Read Write Description 7 0 02h R Minimum Latency The minimum time to complete a burst is 500ns 2 x 0 25us increment 4 1 1 19 Maximum Latency Offset 3Fh Bits POR Read Write Description 7 0 05h R Maximum Latency The maximum time bet...
Страница 24: ...se 0200h 0207h 1 GAMEBase 0208h 020Fh 3 0 R W Adlib Legacy Address Space Enable 0 ADLIBBase disable 1 ADLIBBase enable 2 0 R W Adlib Legacy Address Space Select 0 ADLIBBase 0388h 038Bh 1 ADLIBBase 038Ch 038Fh 1 0 R W SoundBlaster Legacy Address Space Enable 0 SBBase disable 1 SBBase enable 0 0 R W SoundBlaster Legacy Address Space Select 0 SBBase 0220h 022Fh 1 SBBase 0240h 024Fh 4 1 2 3 Legacy DMA...
Страница 25: ...gisters 4 1 3 2 Next Item Pointer Offset 49h Bits POR Read Write Description 7 0 00h R By being 00h indicates the end of the linked list of extended capabilities 4 1 3 3 Power Management Capabilities Offset 4Ah Bits POR Read Write Description 15 11 00000b R PME Support The 4DWAVE DX does not support PME generation 10 1 R D2 Support The 4DWAVE DX supports D2 power state 9 1 R D1 Support The 4DWAVE ...
Страница 26: ... DX does not support PME generation 7 2 000000b R Reserved 1 0 00b R W Power State This is used to determine the current power state Software updates this register when changing power states 00b D0 01b D1 10b D2 11b D3hot 4 1 4 Interrupt Snooping Configuration 4 1 4 1 Interrupt Snooping Control Offset 50h Bits POR Read Write Description 15 8 00h R W Interrupt Vector Compared to vector returned on ...
Страница 27: ...ble 4 2 details the address map of the 4DWAVE DX internal register set These Wave registers are addressable using either the Audio I O Base Address or the Audio Memory Base Address The legacy portion of these registers is available through their respective legacy addresses as well By providing both an I O and a memory aperture to these registers the 4DWAVE DX can be tuned for both compatibility an...
Страница 28: ...SVD 1C SBR10 SBR9 SBR8 SBR8 20 MPUR3 MPUR2 MPUR1 MPUR0 24 2C RSVD Read Only h 00000000 30 RSVD RSVD GAMER1 GAMER0 34 GAMER2 38 GAMER3 3C RSVD Read Only h 00000000 40 ACR0 44 ACR1 48 ACR2 4C RSVD Read Only h 00000000 50 ASR0 54 RSVD ASR2 ASR1 58 ASR3 5C ASR6 ASR5 RSVD ASR4 60 AOPLSR0 64 6C RSVD Read Only h 00000000 70 RSVD RCI2 RCI1 RCI0 74 RSVD Read Only h 00000000 78 PSBVLD_A Channels 0 31 7C PSB...
Страница 29: ... SBBL SBCL C4 SBE2R RSVD SBDD SBCTRL C8 RSVD STIMER CC LFOCTRL_B LFOCOUNT_B ROM_TEST D0 T_FIFO FIFO 39 24 T_FIFO FIFO 19 4 D4 T_DIGIMIXER ADL 19 4 T_DIGIMIXER ADR 19 4 D8 AIN_B Channels 32 63 DC AINTEN_B Channels 32 63 Bank A Address RAM Channels 0 31 E0 CSO ALPHA 11 4 ALPHA 3 0 FMS E4 PSBPTR 1 0 LBA 29 0 E8 ESO DELTA EC RSVD RSVD FMC RVOL 6 1 RVOL 0 CVOL Bank B Address RAM Channel 32 63 E0 CSO AL...
Страница 30: ...DMA Single Channel Mask Port 0Bh DMAR11 000Bh 7 0 00h W Legacy DMA Channel Operation Mode Register 0Ch DMAR12 000Ch 7 0 00h W Legacy DMA First Last Flag Clear Port 0Dh DMAR13 000Dh 7 0 00h W Legacy DMA Master Clear Port 0Eh DMAR14 000Eh 7 0 00h W Legacy DMA Clear Mask Port 0Fh DMAR15 000Fh 7 0 0bh W Legacy DMA Multi Channel Mask Register Legacy SB Mapping Registers 10h SBR0 SBBase 0h 7 0 00h R W L...
Страница 31: ... AudioBase Offset Register Name Bits POR R W Description AC 97 Control Registers 40h ACR0 31 0 00000000h R W AC 97 Codec Write Register 44h ACR1 31 0 00000000h R W AC 97 Codec Read Register 48h ACR2 31 0 00000000h R W AC 97 Command Status Register Miscellaneous Status Control Registers 50h ASR0 31 0 00000000h R 4DWAVE DX Status Register 54h ASR1 15 0 AC44h R Legacy SB Frequency Readback Register 5...
Страница 32: ...rupt Enable Control Register A8h VOL_A 31 0 00008080h R W Global Music Volume and Global Wave Volume Control Register ACh DELTA 31 0 00000000h R W Sample Change Step for Legacy SB Voice In Out Recording B0h MISCINT 31 0 00000000h R W Record Playback Underrun Record Overrun Interrupt Register B4h START_B 31 0 00000000h R W Bank B START Command and Status Register B8h STOP_B 31 0 00000000h R W Bank ...
Страница 33: ...ioBase Offset Register Name Bits POR R W Description E0h CSO Alpha FMS 31 0 XXXXXXXXh R W Current Sample Offset Sample Interpolation Coefficient Frequency Modulation Step E4h PPTR LBA 31 0 XXXXXXXXh R W PSB Pointer Loop Begin Address E8h ESO DELTA 31 0 XXXXXXXXh R W End Sample Offset Delta Sample Rate Ratio ECh FMC RVOL CVOL 31 0 XXXXXXXXh R W FM Control Reverb Volume Chorus Volume Control 4 2 2 4...
Страница 34: ...ss Decode Enable PCI Config 44h bit3 Address Base Select PCI Config 44h bit2 MIDI MPU 401 UART 0330h 0333h or 0300h 0303h Address Decode Enable PCI Config 44h bit7 Address Base Select PCI Config 44h bit6 SoundBlaster 16 0220h 022Fh or 0240h 024Fh Address Decode Enable PCI Config 44h bit1 Address Base Select PCI Config 44h bit0 Game Port 0200h 0207h or 0208h 020Fh Address Decode Enable PCI Config 4...
Страница 35: ...tInput driver loaded the Digital Enhanced Game Port will substantially enhance system and gaming performance by eliminating most of the I O polling overhead up to 12 CPU 4 3 3 5 SoundBlaster DMA The SoundBlaster uses an 8 bit DMA channel In typical system configuration DMA channels 0 1 are available The SoundBlaster will default to channel 1 On 4DWAVE DX channel 0 or 1 can be selected 4DWAVE DX su...
Страница 36: ...0 1 Reserved 0 0 To leave Test Mode the device must be reset with both the TEST 1 0 pins as a logical 1 Both TEST 1 0 pins have an internal Pull Up in the pad 5 2 Global Tristate The Global Tristate test mode will put all outputs into a high impedance state so that no pin is driving a trace This allows system designers to check board trace connectivity or inject input test patterns to other on boa...
Страница 37: ...otes Vcc I O Supply Voltage 4 75 5 25 V Vss I O Ground 0 0 V Vih Input High Voltage 2 0 V 1 Vil Input Low Voltage 0 8 V 1 Voh Output High Voltage 2 4 V 1 Vol Output Low Voltage 0 55 V 1 Note Consistent with both AC 97 Rev 1 13 and PCI 2 1 specifications 6 1 3 I O 3 3V Signaling Environment Symbol Parameter Condition Min Max Units Notes Vcc I O Supply Voltage 3 0 3 6 V Vss I O Ground 0 0 V Vih Inpu...
Страница 38: ...dition Min Max Units Notes Tcyc CLK Cycle Time 30 ns 1 Thigh CLK High Time 11 ns Tlow CLK Low Time 11 ns Tskew CLK Skew 2 ns Note 1 In general all PCI components must work with any clock frequency between DC and 33MHz 2 0V Thigh Tlow Tcyc 1 5V 0 8V 2 4V 0 4V 0 5V 0 4V 0 3V 0 6V 0 2V 5 0 Volt Clock 3 3 Volt Clock 2 0 V p t p minimum 0 4 V p t p minimum ...
Страница 39: ...GNT_N Symbol Parameter Condition Min Max Units Notes Tval_bus CLK to PCI Output Valid Delay bussed signals 2 11 ns Tval_ptp CLK to PCI Output Valid Delay point to point signals 2 12 ns Ton PCI Output float to active 2 ns Toff PCI Output active to float 28 ns Tsu_bus PCI Input set up time to CLK bussed signals 7 ns Tsu_gnt PCI Input set up time to CLK GNT_N 10 ns Tsu_gnt PCI Input set up time to CL...
Страница 40: ...me after CLK stable 100 us Trst_clk RST CLK Power Trst_low 6 2 3 AC 97 Reset Cold and Warm Symbol Parameter Condition Min Max Units Notes Trst_low AC_RESET low time 1 us SW controlled or linked to PCIRST Trst2clk AC_RESET inactive to AC_BITCLK starts 200 ns Tsync_high AC_SYNC high time 1 3 us SW controlled Tsync2clk AC_SYNC inactive to AC_BITCLK starts 200 ns Trst_low AC_BITCLK AC_SYNC AC_RESET Ts...
Страница 41: ...Parameter Condition Min Max Units Notes Tsetup Setup from edge of AC_BITCLK Falling Edge AC0_SDATA_IN AC_SDATA_OUT Rising Edge AC_ SYNC 15 ns Thold Hold from edge of AC0_BITCLK Falling Edge AC0_SDATA_IN AC_SDATA_OUT Rising Edge AC_ SYNC 5 ns AC_BITCLK Thold AC_SYNC AC0_SDATA_IN AC_SDATA_OUT Tsetup Thold Tsetup ...
Страница 42: ...OP IRDY INTR DEVSEL TRDY PERR SERR GD 4 7 GD 0 3 AD 0 31 C BE 0 3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C BE 0 C BE 1 C BE 2 C BE 3 IDSEL PCICLK RESET PAR FRAME STOP IRDY INTR DEVSEL TRDY C1 0 1uF C2 0 1uF C3 0 1uF C4 0 1uF R2 0 R3 0 C7 0 1uF C8 0 1uF C9 0 1uF C10 0 1uF C11 0 1uF U1 4DWA...
Страница 43: ...12 AD11 AD10 AD9 AD8 C BE 0 AD7 AD6 AD5 AD4 C BE 1 AD3 AD2 AD1 AD0 C BE 2 C BE 3 AD 0 31 C BE E 0 3 CON1 PCI32 TRST 1 12V 2 TMS 3 TDI 4 5V 5 INTA 6 INTC 7 5V 8 RSRV9 9 5V_IO 10 R SR V11 11 GND 12 GND 13 R SR V14 14 RST 15 5V_IO 16 GNT 17 GND 18 R SR V19 19 AD30 20 3 3V 21 AD28 22 AD26 23 GND 24 AD24 25 IDSEL 26 3 3V 27 AD22 28 AD20 29 GND 30 AD18 31 AD16 32 3 3V 33 FRAME 34 GND 35 TRDY 36 GND 37 S...
Страница 44: ...ED ON THE BOARD NOTE THIS IS OPTIONAL AMPLIFIER FOR SPEAKER OUT Note Removed Jumpers 4DWAVE 2 layer REV B Schematics converted to ORCADWIN Ver 7 01 No changes from SDT REV B Schematics Dated 2 17 98 spkr1 spkr2 AUDIO_R AUDIO_L 12V C25 100UF C26 470UF C27 470UF L3 FB C28 0 1UF U3 KA2206 IN1 10 NF1 11 BS1 14 OUT1 15 IN2 7 NF2 6 BS2 3 OUT2 2 RR 8 PGND 9 BTLOUT 1 VCC 16 GND 4 GND 5 GND 12 GND 13 C29 1...
Страница 45: ...tems Inc Schematics subject to change without notice JOYSTICK MIDI PORT CONNECTS TO JOYSTICK BODY OF CONNECTOR TO BE GROUNDED This is type DE15 Connector for Joystick GND NOTE Reflects APG Recommendations NOTE R is 2 2K for R84 R85 R86 R87 4DWAVE 2 layer REV B Schematics converted to ORCADWIN Ver 7 01 No changes from SDT REV B Schematics Dated 2 17 98 GD7 GAMEH3 GD6 GAMEH2 GD5 GAMEH1 GD4 GAMEH0 GD...
Страница 46: ...NE_INL AC97_RESET CD_R AGND CD_L AC97D_OUT CD_GND VREFOUT AC97D_IN AC97D_IN AC97_SY NC AC_BITC LK AU X_L AUX_R VREFOUT AUDIO_R spkr1 AUDIO_L spkr2 FB11 FERB 1 2 FB14 FERB 1 2 FB15 FERB 1 2 R49 1K C 124 47n C 125 100n C 126 10u C 129 10u C 131 100n C 132 100n C 135 1u JP1 PC SPEAKER C 136 1n R59 47K J3 LINEINPUT 2 3 4 5 1 R61 0 C 128 10u C 127 10u FB12 FERB 1 2 C 134 100n C 133 100n J1 LINEOUTPUT 2...
Страница 47: ...eramic 50V SMD 0805 Load For Amplifier Default No LOAD 4 6 C12 C13 C14 C15 C22 C153 10UF Cap 25V Radial Thru Hole 5a 6 C25 C31 C32 C33 C34 C35 100UF Cap 16V Radial Thru Hole Load For Amplifier Default No LOAD 5b 2 C41 C153 100UF Cap 16V Radial Thru Hole 6 12 C26 C27 470uF Cap 16V Can Thru Hole Load For Amplifier Default No LOAD 7 3 C29 C30 C105 C107 C110 C111 C116 C117 C118 C121 C122 C135 C155 1uF...
Страница 48: ...D1 D2 1N4001 Thru Hole axial Load For Amplifier Default No LOAD 17a 2 FB3 FB5 1 FERB Axial Ferrite Bead Load One only Default is FB5 17b 11 FB10 FB11 FB12 FB13 FB14 FB15 FB16 FB17 FB18 FB19 FB20 FERB Axial Ferrite Bead Load For Amplifier Default No LOAD 18 1 JP1 PC SPEAKER Header 1X2 Header 19 3 JP2 JP3 JP4 HEADER 4 1X4 Header For CD ROM 20 2 JP7 JP8 HEADER 3 Jumper with Shunt For Selecting Lineou...
Страница 49: ... R16 15K Resistor 1 10W SMD 0805 5 Load For Amplifier Default No LOAD 28a 2 R15 R17 10K Resistor 1 10W SMD 0805 5 Load For Amplifier Default No LOAD 28b 8 R28 R64 R88 R89 R90 R91 R100 R1012 10K Resistor 1 10W SMD 0805 5 29 2 R18 R19 1 2K Resistor 1 10W SMD 0805 5 Load For Amplifier Default No LOAD 30 2 R27 R29 47 Resistor 1 10W SMD 0805 5 31 6 R49 R50 R53 R54 R57 R58 1K Resistor 1 10W SMD 0805 5 3...
Страница 50: ... 35 1 U1 4DWAVE 100 pin LQFP Trident Audio Chip 36 1 U2 LT1587C M 3 3 Voltage Regulator Do Not Load 37 1 U2A AME8613 3 UP Voltage Regulator Load 38 1 U3 KA2206 Power Amp DIP DO NOT LOAD 39 1 U4 AC97 1 ADI 1819A AC97 CODEC Trident Approved 40 1 Y2 24 576MH z Cardinal Crystal NOTE All Items in BOLD and Italics are components associated with Power Amplifier We do not recommend populating these ...
