18/09/2003
HESC-UPS Manual
Tri-M Engineering
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8
where "host" addressW = 0001 001 + 0 (R/W bit) = 0x12
"host" addressR = 0001 001 + 1 (R/W bit) = 0x13
The checksum is a two digit hexadecimal checksum that is the two's complement of the sum of all preceding
bytes. For example the data <0x10> <0x12> <0xC0> <0x03> has the checksum 0x1B.
Section 4 : HESC104 PC/104 Bus Communications
A. Description:
The HESC104 communicates with the Host through the PC/104 bus. Commands and data are sent and received using a
8 bit, I/O memory mapped I/O address. The address lines A0 to A9, & AEN are decoded to provide four addresses that
are jumper selectable. An I/O write to the decoded address will "strobe" the data into the HESC, and an I/O read will read
the data from the HESC104. Whenever the HESC104 has data in it's output port that requires the Host CPU to perform
an I/O read, it generates a PC/104 bus interrupt (IRQ5 or IRQ7, see section on setting jumpers). The PC/104 bus
interrupt is removed after an I/O read from the HESC104. The HESC104 operates in a "slave" mode where the Host
initiates all the communications between the HESC104 and the Host.
- Table 1 lists the commands the HESC supports.
To ensure reliable communication, an acknowledge byte is returned after each address, command or data byte
transmitted. The receiving device (HESC104 or Host) must acknowledge receipt of each byte. This is true even if the bus
timer is turned off.
(The HESC104 and HESC-SER differ in that if the HESC-SER bus timer is off an acknowledge byte is
not issued.)
If an acknowledge byte doesn't match the acknowledge number expected then a "collision" is deemed to have
occurred. The transaction is aborted immediately and the result byte set accordingly.
An "enhanced" communication mode is available by adding an optional checksum value. If the HESC104 receives a
Read command from the Host with the acknowledge set to 0x03 after sending [databyteR high], it will switch to enhanced
mode for all future communications. Communication will return to non-checksum mode when the Host CPU sends an
acknowledge 0xFF after [databyteR high].
B. Slave Mode:
1. Commands received from the Host and data sent to or received from the to Host CPU over the PC/104 bus. The
transaction is invalid and commands/data are not to be used until:
-
the final acknowledge 0xFF is received
-
the checksum matches the transmitted data (checksum is optional, but if sent must be used)
2. Note: Read and Write is defined as the action the command places on the HESC104's RAM and EEprom. Therefore,
Read and Write have the same meaning for Master and Slave modes:
3a. Write command without checksum acknowledge.
HOST: <addressW> <command> <databyteW low > <databyteW high >
HESC104: [0x00] [0x01] [0x02] [0xFF]
3b. Write command with checksum acknowledge.
HOST: <addressW> <command> <databyteW low > <databyteW high > <checksum>
HESC104: [0x00] [0x01] [0x02] [0x03] [0xFF]
4a. Read command without checksum acknowledge.
HOST: <addressR> <command> <0x02> <0xFF>
HESC104: [0x00] [databyteR low] [databyteR high]
