TE0712 TRM
Revision: V14
Copyright © 2017 Trenz Electronic GmbH
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http://www.trenz-electronic.de
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank
B2B Connector
I/O Signal Count
Voltage Level
Notes
13
JM1
10
VCCIO13
Supplied by the baseboard.
13
JM3
20
VCCIO13
Supplied by the baseboard.
14
JM1
8
3.3V
14
JM2
18
3.3V
14
JM3
4
3.3V
15
JM2
48
VCCIO15
Supplied by the baseboard.
15
JM2
2
VCCIO15
Supplied by the baseboard.
16
JM1
48
VCCIO16
Supplied by the baseboard.
Please refer to the
tables page for additional information.
JTAG Interface
JTAG access to the Xilinx Artix-7 FPGA and System Controller CPLD devices is provided through B2B
connector JM2.
JTAG Signal
B2B Pin
TMS
JM2-93
TDI
JM2-95
TDO
JM2-97
TCK
JM2-99
JTAGEN pin in B2B connector JM1 is used to select JTAG access for FPGA or SC CPLD:
JTAGEN
JTAG Access To
Low
Artix-7 FPGA
High
System Controller CPLD