Transmeta Crusoe TM5500, Руководство по проектированию систем

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July 17, 2002
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SDR Memory Design
5.3.5 Uncertainty in the Feedback Calculation
The JEDEC specification is very specific about the layout of the clock trace on the SODIMM, but only gives
the total length of the other lines, including data. There will also be some variation of capacitive delays in
boards due to geometry, number of vias, etc. There may also be some variation in the actual delays of data
and clock lines depending on how well the designer controls the return path integrity.
To address delay variation possibilities, a structure in the CLKIN feedback path that allows for some
adjustment of the final configuration is strongly recommended. As shown in Figure 12, zero
Ω
jumpers can
be used to add or remove delays from the line. Testing can be done during the prototyping stage to determine
the optimum delay setting. For manufacturing, either the bill-of-materials (BOM) can be selected to give the
optimum delay, or the board layout can be revised to remove the unneeded jumpers and delay elements.
5.3.6 Using Soldered-down Memory
The previous sections have established the basis for an effective layout of the SDR SDRAM subsystem in a
TM5500/TM5800 processor-based system. However, the method discussed requires the use of two
SODIMMs. Code Morphing software cannot dynamically configure memory, and if a factory-installed memory
module is replaced by a different module, Code Morphing software could fail to load or operate reliably.
Another memory solution possibility uses soldered-down memory on the system motherboard. It is often
desirable to place one or two banks of memory on the motherboard to provide a minimum system memory
configuration and assure that Code Morphing software can always operate in this permanent memory
section.
The design approach for soldered-down memory is straightforward. Having established that the two SODIMM
design method previously discussed delivers optimal performance, soldered-down memory can be treated
from the design perspective
as if it was an SODIMM , using exactly the same routing topology used for the all-
SODIMM solution. This topology results in a component placement that keeps the SODIMM connector and
the on-board SDRAM in close proximity, as shown in Figure 13 and Figure 14.
The layout in Figure 13 is the simplest from a routing perspective. Signals are routed from the processor to
the SODIMM connector and then to the on-board SDR SDRAM (passing through any needed termination
resistors on the way). If the SODIMM connector is facing the other direction, as shown in Figure 14, the
traces are routed from the processor to the connector, then back to the SDR SDRAM chips. In this sub-
optimal placement, routing congestion occurs, possibly increasing the number of required board layers.
Figure 12: Adjustment of CLKIN Delay
CLKOUT
CLKIN
R
T
0 0
0
0
0
0
0
0
0
Calculated Delay of SCLKIN
250 psec 250 psec 250 psec