T
T
T
S
S
S
6
6
6
4
4
4
G
G
G
S
S
S
S
S
S
D
D
D
1
1
1
0
0
0
-
-
-
M
M
M
1.0” Solid State Disk
Transcend Information Inc.
V1.6
13
True IDE PIO Mode Read/Write Timing Specification
Mode
Item
0
1
2
3
4
Note
t0
Cycle time (min)
600
383
240
180
120
1
t1
Address Valid to -HIOR/-HIOW setup (min)
70
50
30
30
25
t2
-HIOR/-HIOW (min)
165
125
100
80
70
1
t2
-HIOR/-HIOW (min) Register (8 bit)
290
290
290
80
70
1
t2i
-HIOR/-HIOW recovery time (min)
-
-
-
70
25
1
t3
-HIOW data setup (min)
60
45
30
30
20
t4
-HIOW data hold (min)
30
20
15
10
10
t5
-HIOR data setup (min)
50
35
20
20
20
t6
-HIOR data hold (min)
5
5
5
5
5
t6Z
-HIOR data tristate (max)
30
30
30
30
30
2
t9
-HIOR/-HIOW to address valid hold
20
15
10
10
10
tRD
Read Data Valid to DSTROBE active (min),
if DSTROBE initially low after tA
0
0
0
0
0
tA
DSTROBE Setup time
35
35
35
35
35
3
tB
DSTROBE Pulse Width (max)
1250
1250
1250
1250 1250
tC
DSTROBE assertion to release (max)
5
5
5
5
5
Notes: All timings are in nanoseconds. All time intervals are recorded in nanoseconds. Although minimum time from DSTROBE high
to HIOR# high is 0 nsec, the minimum HIOR# width is still met.
1) Where t0 denotes the minimum total cycle time, t2 represents the minimum command active time, and t2i is the minimum
command recovery time or command inactive time. Actual cycle time equals the sum of the actual command active time and
the actual command inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time
requirement is greater than the sum of t2 and t2i, implying that a host implementation can extend either or both t2 or t2i to
ensure that t0 is equal to or greater than the value reported in the device’s identify device data. A PATA implementation
supports any legal host implementation.
2) This parameter specifies the time from the negation edge of HIOR# to the time that the PATA (tri-state) no longer drives the
data bus.
3) The delay from the activation of HIOR# or HIOW# activation until the state of DSTROBE is first sampled. If DSTROBE is
inactive, the host waits until DSTROBE is active before the PIO cycle is completed. When the PATA is not driving DSTROBE,
which is negated at the tA after HIOR# or HIOW# activation, then t5 is met and tRD is not applicable. When the PATA is
driving DSTROBE, which is negated at the time tA after HIOR# or HIOW#, then tRD is met and t5 is not applicable.
4) DSTROBE is not supported in this mode.
