User's Manual l TQMxE39S UM 0101 l © 2019 TQ-Group
Page 20
SMARC Connector Pin Assignment (continued)
Pin
Pin-Signal
Description
Type
Level
Remark
S105
DP++ AUX Channel (could also be used as 3.3 V I
2
C for HDMI)
IO
DP++ /3.3 V PU at high AUX_SEL
S106 DP0_AUX–
DP++ AUX Channel (could also be used as 3.3 V I
2
C for HDMI)
IO
DP++ /3.3 V PU at high AUX_SEL
S107 LCD1_BKLT_EN
LCD Backlight enable: high enables panel backlight
O
1.8 V
N/A
S108 L / e / D
LVDS LCD differential clock pair / eDP AUX Channel
O/IO
LVDS/DP
LVDS only
S109 LVDS1_CK– / eDP1_AUX– / DSI1_CLK–
LVDS LCD differential clock pair / eDP AUX Channel
O/IO
LVDS/DP
LVDS only
S110 GND
Ground
GND
S111 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S112 LVDS1_0– / eDP1_TX0– / DSI1_D0–
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S113 eDP1_HPD
eDP Hot Plug Detect
I PD
1.8 V
N/A
S114 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S115 LVDS1_1– / eDP1_TX1– / DSI1_D1–
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S116 LCD1_VDD_EN
Enable signal for panel power
O
1.8 V
N/A
S117 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S118 LVDS1_2– / eDP1_TX2– / DSI1_D2–
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S119 GND
Ground
GND
S120 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S121 LVDS1_3– / eDP1_TX3– / DSI1_D3–
LVDS / eDP data differential pair /
O
LVDS/DP
LVDS only
S122 LCD1_BKLT_PWM
Display Backlight brightness control output (PWM)
O
1.8 V
N/A
S123 RSVD
Reserved
S124 GND
Ground
GND
S125 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
S126 LVDS0_0– / eDP0_TX0– / DSI0_D0–
LVDS / eDP data differential pair /
O
LVDS/DP
S127 LCD0_BKLT_EN
LCD Backlight enable: high enables panel backlight
O
1.8 V
S128 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
S129 LVDS0_1– / eDP0_TX1– / DSI0_D1–
LVDS / eDP data differential pair /
O
LVDS/DP
S130 GND
Ground
GND
S131 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
S132 LVDS0_2– / eDP0_TX2– / DSI0_D2–
LVDS / eDP data differential pair /
O
LVDS/DP
S133 LCD0_VDD_EN
Enable signal for panel power
O
1.8 V
S134 L / e / D
LVDS LCD differential clock pair / eDP AUX Channel
O/IO
LVDS/DP
S135 LVDS0_CK– / eDP0_AUX– / DSI0_CLK–
LVDS LCD differential clock pair / eDP AUX Channel
O/IO
LVDS/DP
S136 GND
Ground
GND
S137 / e /
LVDS / eDP data differential pair /
O
LVDS/DP
S138 LVDS0_3– / eDP0_TX3– / DSI0_D3–
LVDS / eDP data differential pair /
O
LVDS/DP
S139 I2C_LCD_CK
I
2
C bus to read display EDID EEPROMs (for LVDS displays)
IO PU 1.8 V
S140 I2C_LCD_DAT
I
2
C bus to read display EDID EEPROMs (for LVDS displays)
IO PU 1.8 V
S141 LCD0_BKLT_PWM
Display Backlight brightness control output (PWM)
O
1.8 V
S142 RSVD
Reserved
S143 GND
Ground
GND
S144 eDP0_HPD
eDP Hot Plug Detect
I PD
1.8 V
S145 WDT_TIME_OUT#
Watch-Dog-Timer Output
O
1.8 V
S146 PCIE_WAKE#
PCIe wake up interrupt to host
I PU
3.3 V
5
S147 VDD_RTC
Real-time clock circuit-power input
PWR
2 V to 3.3 V
S148 LID#
Lid open/close indication to module (low indicates closed lid)
I PU
1.8 V
S149 SLEEP#
Sleep indicator from carrier board
I PU
1.8 V
S150 VIN_PWR_BAD#
Power bad indication from Carrier board
I PU
VDD_IN
S151 CHARGING#
Held low by carrier during battery charging
I PU
1.8 V
5
S152 CHARGER_PRSNT#
Held low by carrier if DC input for battery charger is present
I PU
1.8 V
S153 CARRIER_STBY#
Driven low by module during standby power state. (SUS_S3#)
O
1.8 V
S154 CARRIER_PWR_ON
Signal to carrier to turn on determined power supplies (SUS_S5#)
O
1.8 V
5
S155 FORCE_RECOV#
Force recovery input: pull low to load BIOS defaults
I PU
1.8 V
S156 BATLOW#
Battery low indication to module
I PU
1.8 V
5:
Configurable through TQ-flexiCFG.
