User's Manual l TQMLS10xxA UM 0105 l © 2022, TQ-Systems GmbH
Page 9
4.2
Reset Configuration Word RCW
The Reset Configuration Word RCW can be taken from the LS1043A / LS1046A / LS1088A Reference Manuals (1).
4.3
RCW source selection
On the TQMLS10xxA the RCW source selection is controlled by a CPLD. An external pin strapping is not required.
BOOT_
SRC[0:1]
Pin-Strapping
- Active driver during RESET#
- High-Z during normal operation
IFC
BUS
PORESET#
Board
Controller
RESIN#
LS CPU
CPLD
TQMLS10xxA
connectors
Figure 5:
Block diagram RCW source selection
The boot source is selected with signals BOOT_CFG[1:0].
Table 3:
RCW source selection
BOOT_CFG1
BOOT_CFG0
RCW Source
Low
Low
QSPI NOR Flash
Low
High
I
2
C (LS1088A only)
High
Low
SDHC
High
High
eMMC
BOOT_CFG[1:0] is initialized with a Pull-Up to 3.3V on the TQMLS10xxA.
After the TQMLS10xxA is powered-up, the CPLD applies the pin strapping.
4.4
Clock supply
The clock supply on the TQMLS10xxA corresponds to the structure „Multiple Reference clocking“, described in (1).
•
SYSCLK = 100 MHz
•
DDRCLK = 100 MHz (LS1043A, LS1046A), 133.33 MHz (LS1088A)
•
ECx_GTX_CLK125 is not generated on the TQMLS10xxA, has to be generated externally.
•
Differential SERDES clocks are not generated on the TQMLS10xxA, have to be generated externally.
4.5
Power Modes
Currently no power modes are implemented.
