User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH
Page 21
4.2.2
USB 2.0 Hi-Speed Host
The TUSB8041l provides a chip-to-chip connection via USB2.0 to the USB2.0 hub, which is configured via the I2C4 bus.
The USB hub USB4604I provides four USB 2.0 Hi-Speed Host interfaces. The hub has one upstream port and four downstream
ports. USB Host1&2 are routed to display connectors X55 and X56. Host3 is available at the SATA M.2 connector X26, and Host4 is
available at the mPCIe connector X29.
The USB Host port of the TQMa57xx provides a theoretical data rate of 480 Mbit/s. The data rate is shared amongst the
connected ports. The data rates of the ports can significantly deviate depending on the hardware and software used.
Illustration 10:
Block diagram USB 2.0 Hosts
The following tables show the pin assignment of the connectors used.
Table 19:
Pinout X55, USB 2.0 Host1
Pin
Pin name
Signal
Dir.
Remark
13
D–
USB2.0_H1_D_N
I/O
Common Mode Choke in series
14
D+
USB2.0_H1_D_P
I/O
Common Mode Choke in series
Table 20:
Pinout X56, USB 2.0 Host2
Pin
Pin name
Signal
Dir.
Remark
36
D–
USB2.0_H2_D_N
I/O
Common Mode Choke in series
38
D+
USB2.0_H2_D_P
I/O
Common Mode Choke in series
Table 21:
Pinout X26, USB 2.0 Host3
Pin
Pin name
Signal
Dir.
Remark
9
D–
USB2.0_H3_SATA_N
I/O
Common Mode Choke in series
7
D+
USB2.0_H3_SATA_P
I/O
Common Mode Choke in series
Table 22:
Pinout X29, USB 2.0 Host4
Pin
Pin name
Signal
Dir.
Remark
36
D–
USB2.0_H4_MPCIE_N
I/O
Common Mode Choke in series
38
D+
USB2.0_H4_MPCIE_P
I/O
Common Mode Choke in series
