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User's Manual  l  TQMa6x & TQMa6xP UM 0403  l  © 2019, TQ-Systems GmbH 

 

Page  35 

 

3.2.7.4

 

Power-Up sequence TQMa6x / carrier board 

The TQMa6x operates with 5 V; the 3.3 V I/O voltages of the i.MX6 signals are generated on the TQMa6x. 
This leads to requirements for the carrier board design concerning the chronological characteristics of the voltages generated on 

the carrier board. 
 
 

Note: Power-Up sequence on the carrier board 

 

To ensure a correct Power-Up, the following sequence must be met on the carrier board: 
The supply voltage of 5 V for the TQMa6x is present and the carrier board supply of 3.3 V  

is activated by TQMa6x pin VCC3V3MB_EN (X2–26). 

 
 
The following block diagram shows how VCC3V3MB_EN controls the voltage regulator on a carrier board. 
 

TQMa6x

DC/DC 3V3

Startup time 

≤

12 ms

VCC5V

VCC3V3MB_EN

ENABLE

VIN

VOUT

VIN

5 V

3.3 V

 

Illustration 17:  Block diagram power supply carrier board 

 
No modifications need to be made to carrier boards developed for TQMa6x revision 01xx using pin VCC3V3_REF_OUT (X2-56)  

to activate the 3.3 V controller. 
For re-designs or new designs, however, signal VCC3V3MB_EN (X2-26), available as of TQMa6x revision 02xx, is recommended. 
 
 

Attention: Power-Up sequence 

 

To avoid cross-supply and errors in the power-up sequence, no I/O pins may be driven by external 

components until the power-up sequence has been completed. 
The end of the power-up sequence is indicated by a high level of signal VCC3V3MB_EN. 

 
 

3.3

 

TQMa6x interface 

3.3.1

 

Pin multiplexing 

When using the i.MX6 signals, the multiple pin configurations by different i.MX6-internal function units must be taken note of.  

The pin assignment listed in Table 50, Table 51 and Table 52 refer to the corresponding 

BSP provided by TQ-Systems GmbH

  

in combination with the Starterkit MBa6x. The electrical and pin characteristics are to be taken from the i.MX6 and PMIC 

documentation (1), (2), (3), (4), (5), (6), and (10). 
 
 

Attention: Malfunction or destruction 

 

Depending on the configuration, many of the i.MX6 pins can provide several different functions. 
Please take note of the information in the i.MX6 Reference Manuals (4), (5), and (6), concerning the 

configuration of these pins before integration or start-up of your carrier board / Starterkit. 
Improper programming by operating software can cause malfunctions, deterioration or destruction  
of the TQMa6x. 

 

Содержание TQMa6x

Страница 1: ...TQMa6x TQMa6xP User s Manual TQMa6x TQMa6xP UM 0403 19 09 2019...

Страница 2: ...3 2 1 1 i MX6 derivatives 6 3 2 1 2 eFUSEs 6 3 2 1 3 i MX6 errata 6 3 2 1 4 Boot modes 7 3 2 1 5 Boot configuration 8 3 2 1 6 Boot interfaces 9 3 2 1 7 Boot device eMMC 9 3 2 1 8 Boot device SPI NOR...

Страница 3: ...out differences connector X2 TQMa6x Rev 02xx Rev 04xx 40 4 MECHANICS 41 4 1 Connectors 41 4 2 Dimensions 41 4 3 Component placement 43 4 4 Adaptation to the environment 44 4 5 Protection against exter...

Страница 4: ...15 Table 17 Temperature sensor 15 Table 18 Internally used interfaces 16 Table 19 Externally available interfaces 16 Table 20 Signals AUD3 17 Table 21 Signals CCM 17 Table 22 Signals ECSPI1 ECSPI5 17...

Страница 5: ...MX6 6 Illustration 3 Block diagram DDR3L SDRAM connection 12 Illustration 4 Block diagram eMMC NAND flash connection 13 Illustration 5 Block diagram SPI NOR flash connection 13 Illustration 6 Block d...

Страница 6: ...ble 10 3 2 7 4 3 2 5 23 6 5 Illustration 22 Table 58 Table 59 Formatting links updated Clocks corrected Warning updated Updated Package temperature replaced with Case temperature Case temperature DDR3...

Страница 7: ...and trademarks are rightly protected by a third party 1 3 Disclaimer TQ Systems GmbH does not guarantee that the information in this User s Manual is up to date correct complete or of good quality No...

Страница 8: ...ortant details or aspects for working with TQ products Command A font with fixed width is used to denote commands contents file names or menu items 1 7 Handling and ESD tips General handling of your T...

Страница 9: ...nts used for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable operation These documents are stored...

Страница 10: ...characteristics NXP i MX6 Solo DualLite Dual Quad DualPlus QuadPlus Up to 2 Gbyte DDR3L SDRAM 64 bit interface except Solo 32 bit interface Up to 8 Gbyte eMMC NAND flash Up to 128 Mbyte SPI NOR flash...

Страница 11: ...S PDIF 2 CAN 2 General Purpose Clocks 2 I2 C 2 LVDS display 2 SPI 2 USB 2 0 Hi Speed 1 USB Host 1 USB OTG 40 GPIO 4 PWM 4 UART with Handshake Further interfaces of the i MX6 are also available as an a...

Страница 12: ...C to 105 C Yes i MX6Q Quad Industrial 800 MHz 40 C to 105 C Yes i MX6DP DualPlus Industrial 800 MHz 40 C to 105 C Yes i MX6QP QuadPlus Industrial 800 MHz 40 C to 105 C Yes 3 2 1 2 eFUSEs The eFUSEs in...

Страница 13: ...ides two possibilities Burning internal eFuses Reading dedicated GPIO pins The exact behaviour during booting depends on the value of the register BT_FUSE_SEL The following table shows the behaviour o...

Страница 14: ...g 11 Reserved Solo DualLite Dual Quad 11 Extension Mode DualPlus QuadPlus see BOOT_CFG3 1 0 0 BOOT_CFG3_5 X2 99 BOOT_CFG3 4 0 BOOT_CFG3_4 X2 100 BOOT_CFG3 3 Reserved 0 BOOT_CFG3_3 X2 101 BOOT_CFG3 2 B...

Страница 15: ...nabled 1 BOOT_CFG1_1 X2 121 BOOT_CFG2 7 eMMC Bus Width 000 1 bit 001 4 bit 010 8 bit 101 4 bit DDR MMC 4 4 110 8 bit DDR MMC 4 4 0 BOOT_CFG2_7 X2 107 BOOT_CFG2 6 1 BOOT_CFG2_6 X2 108 BOOT_CFG2 5 0 BOO...

Страница 16: ...4 5 CS select SPI only 00 CS 0 01 CS 1 10 CS 2 11 CS 3 0 BOOT_CFG4_5 X2 89 BOOT_CFG4 4 1 BOOT_CFG4_4 X2 90 BOOT_CFG4 3 SPI Addressing SPI only 0 2 bytes 16 bit 3 75 MHz Clock 1 3 Bytes 24 bit 15 MHz C...

Страница 17: ...121 BOOT_CFG1 0 SD Loopback Clock Source Sel for SDR50 and SDR104 only 0 through SD pad 1 direct 0 BOOT_CFG1_0 X2 122 BOOT_CFG2 7 SD Calibration Step 00 1 delay cell 01 1 delay cell 10 2 delay cell 1...

Страница 18: ...memory interface depend on the i MX6 derivative The following table shows the different possibilities Table 10 i MX6 SDRAM interface according to i MX6 derivative i MX6 derivative Bus width Clock SDR...

Страница 19: ...he following block diagram shows how the SPI NOR flash is connected to the i MX6 i MX6 SPI NOR flash ECSPI1_SCK ECSPI1_SS1 C S ECSPI1_MOSI DQ0 DQ1 ECSPI1_MISO W Connector X3 40 SPI NOR_WP 10 k VCC3V3...

Страница 20: ...hows the EEPROM used Table 14 EEPROM component Manufacturer Part number Size Temperature range STM M24C64 WDW6TP 64 kbit 45 C to 85 C The I2 C address of the EEPROM is 0x50 101 0000b In the EEPROM TQM...

Страница 21: ...option depending on the use case It is to be taken note of that the typical charging current is only 60 A For long term bridging an external RTC connected at the I2 C bus on the carrier board is reco...

Страница 22: ...d EPIT 2 Secondary EPIT1 EPIT2 Multiplexing has to be adapted ESAI 1 Secondary Multiplexing has to be adapted FLEXCAN 2 Primary 3 2 5 6 FLEXCAN1 FLEXCAN2 GPIO 40 Primary 3 2 5 7 GPMI 1 Secondary Multi...

Страница 23: ...5 and 6 3 2 5 3 CCM The i MX6 clock controller CCM provides two programmable clocks The following table shows the signals of the CCM Table 21 Signals CCM Signal name Direction i MX6 ball TQMa6x Remark...

Страница 24: ...24 X2 44 RGMII_TD2 O E21 X2 42 RGMII_TD1 O F20 X2 40 RGMII_TD0 O C22 X2 38 RGMII_TX_CTL O C23 X2 46 RGMII_TXC O D21 X2 34 Note NVCC_ENET NVCC_ENET_IN has to be connected externally The RGMII interface...

Страница 25: ...ced ENET performance On account of the NXP erratum ERR006687 which describes reduced ENET performance when responding to interrupts new variants were introduced with TQMa6x revision 04xx The workaroun...

Страница 26: ...ction i MX6 ball TQMa6x Remark GPIO1_IO5 I O R4 X1 86 Only on Variant C see Illustration 11 GPIO1_IO30 I O U20 X1 149 GPIO1_IO29 I O W20 X1 151 GPIO1_IO28 I O V21 X1 153 GPIO1_IO26 I O W22 X1 154 GPIO...

Страница 27: ...d by the I2 C interfaces Table 28 Signals I2 C Signal name Dir i MX6 ball TQMa6x Remark I2C1_SCL O N5 X1 107 4 7 k PU to 3 3 V on TQMa6x no PU on Variant B see Illustration 10 I2C1_SDA I O N6 X1 109 4...

Страница 28: ...2 x I2C1 ENET Ping Patch Standard variant for Solo DualLite Dual and Quad Illustration 9 ENET Patch Variant A TQMa6x 04xx Variant B is also fully backward compatible HW SW with designs based on TQMa6...

Страница 29: ...148 Display Output RGB Data i MX6 signal IPU1_DISP0_DATA13 DISP0_DAT12 O T24 X2 147 Display Output RGB Data i MX6 signal IPU1_DISP0_DATA12 DISP0_DAT11 O T23 X2 144 Display Output RGB Data i MX6 signa...

Страница 30: ...all TQMa6x LVDS0_CLK_P O V3 X1 138 LVDS0_CLK_N O V4 X1 136 LVDS0_TX3_P O W1 X1 144 LVDS0_TX3_N O W2 X1 142 LVDS0_TX2_P O V1 X1 132 LVDS0_TX2_N O V2 X1 130 LVDS0_TX1_P O U3 X1 126 LVDS0_TX1_N O U4 X1 1...

Страница 31: ...rovides a MIPI Display Serial Interface DSI which is routed to connector X3 The following table shows the signals used by the MIPI_DSI interface Table 33 Signals MIPI_DSI Signal name Direction i MX6 b...

Страница 32: ...ial clock see 3 2 5 26 3 2 5 17 PWM The i MX6 provides several PWMs which are routed to the connectors The following table shows the available PWM signals Table 36 Signals PWM Signal name Direction i...

Страница 33: ...MX6 internal PU 47 k JTAG_TDO O G6 X1 73 i MX6 internal keeper JTAG_TRST I C2 X1 67 i MX6 internal PU 47 k JTAG_MOD I H6 X1 75 4 7 k PD on TQMa6x i MX6 internal 100 k PU 3 2 5 20 S PDIF The i MX6 pro...

Страница 34: ...ration 12 Block diagram UART interfaces The following table shows the signals used by the UART interfaces Table 42 Signals UARTs Signal name Direction i MX6 ball TQMa6x Remark UART5_TXD O M4 X1 91 UAR...

Страница 35: ...by the USB_OTG interface Table 44 Signals USB_OTG Signal name Direction i MX6 ball TQMa6x Remark USB_OTG_DP I O A6 X1 49 USB_OTG_DN I O B6 X1 51 USB_OTG_ID I T4 X1 45 Device Mode Connect to Micro USB...

Страница 36: ...Reference Manuals 4 5 and 6 Watchdog timer If the watchdog timer is activated and is not reset within the configured time signal WDOG1 is activated At the same time the i MX6 System Reset Controller...

Страница 37: ...lustration 13 Block diagram Reset The following table describes the reset signals available at the connectors Table 48 Reset signals Signal name i MX6 ball TQMa6x Direction Remark MX6_POR C12 X2 23 IP...

Страница 38: ...single pins and signals are to be taken from the PMIC data sheet 10 or the i MX6 Reference Manuals 4 5 and 6 The following block diagram shows the circuitry between PMIC and i MX6 Connector X2 PMIC C...

Страница 39: ...Supervisor DCDC4V2 RESET EN VCC5V PMIC VCC4V2 VIN TQM_PWR_OFF MR Illustration 16 Block diagram VCC5V monitoring With signal TQM_PWR_OFF the TQMa6x can be switched off completely This ensures the lowes...

Страница 40: ...1591 mA 7 96 W Theoretical value TQMa6U i MX6DualLite U Boot prompt Not measured Linux prompt Not measured Linux 100 CPU load Not measured Calculated peak 2251 mA 11 26 W Theoretical value TQMa6D i M...

Страница 41: ...s or new designs however signal VCC3V3MB_EN X2 26 available as of TQMa6x revision 02xx is recommended Attention Power Up sequence To avoid cross supply and errors in the power up sequence no I O pins...

Страница 42: ...38 HDMI_CLK_N HDMI 18 O J5 T5 O 3 3 V USB USB_H1_PWR 39 40 HDMI_CLK_P HDMI 18 O J6 R7 I 3 3 V USB USB_H1_OC 41 42 DGND POWER 0 V P E9 P 5 V POWER USB_OTG_VBUS 43 44 HDMI_D0_N HDMI 18 O K5 T4 I 3 3 V U...

Страница 43: ...GND POWER 0 V P Y1 O 21 LVDS LVDS1_TX0_N 117 118 LVDS0_TX0_N LVDS 21 O U2 Y2 O 21 LVDS LVDS1_TX0_P 119 120 LVDS0_TX0_P LVDS 21 O U1 P 0 V POWER DGND 121 122 DGND POWER 0 V P AA2 O 21 LVDS LVDS1_TX1_N...

Страница 44: ...RGMII_RD3 43 44 RGMII_TD3 RGMII 2 5 V O A24 D22 I 2 5 V RGMII RGMII_RX_CTL 45 46 RGMII_TX_CTL RGMII 2 5 V O C23 P 0 V POWER DGND 47 48 DGND POWER 0 V P V20 O ENET MII ENET_MDC 24 49 50 ENET_REFCLK 24...

Страница 45: ...T 3 3 V 27 I L24 L25 I 3 3 V 27 BOOT BOOT_CFG1_7 115 116 BOOT_CFG1_6 BOOT 3 3 V 27 I K25 L23 I 3 3 V 27 BOOT BOOT_CFG1_5 117 118 BOOT_CFG1_4 BOOT 3 3 V 27 I L22 K24 I 3 3 V 27 BOOT BOOT_CFG1_3 119 120...

Страница 46: ...0 V P F2 I 28 MIPI CSI CSI_D3_N 27 28 DSI_D0_N MIPI DSI 28 O G2 F1 I 28 MIPI CSI CSI_D3_P 29 30 DSI_D0_P MIPI DSI 28 O G1 P 0 V POWER DGND 31 32 DGND POWER 0 V P C5 O 2 5 V XTAL CLK2_N 33 34 DSI_D1_N...

Страница 47: ...See chapter 4 8 for further information The following table shows some suitable mating connectors for the carrier board Table 55 Carrier board mating connectors Manufacturer Part number Remark Stack h...

Страница 48: ...User s Manual l TQMa6x TQMa6xP UM 0403 l 2019 TQ Systems GmbH Page 42 4 2 Dimensions continued Illustration 19 TQMa6x dimensions top view Illustration 20 TQMa6x dimensions top view through TQMa6x...

Страница 49: ...component placement top The labels on the TQMa6x show the following information Table 57 Labels on TQMa6x Label Text AK1 TQMa6x version and revision AK2 MAC address additional reserved MAC addresses t...

Страница 50: ...gory in which a cooling system is essential It is the user s sole responsibility to define a suitable heat sink weight and mounting position depending on the specific mode of operation e g dependence...

Страница 51: ...oltages Fast or permanent clocked lines e g clock should be kept short avoid interference of other signals by distance and or shielding Take note of not only the frequency but also the signal rise tim...

Страница 52: ...mental temperature i MX6 40 C to 85 C Chip temperature PMIC 40 C to 125 C Environmental temperature PMIC 40 C to 85 C Case temperature DDR3L SDRAM 40 C to 95 C Case temperature other ICs 25 C to 85 C...

Страница 53: ...quency ranges 2 9 Hz 9 200 Hz 200 500 Hz Wobble rate 1 0 octaves min Excitation axes X Y Z axis Amplitude 2 Hz 9 Hz 3 5 ms 2 9 Hz 200 Hz 10 ms 2 200 Hz 500 Hz 15 ms 2 6 6 Reliability and service life...

Страница 54: ...on the TQMa6x 6 7 6 Packaging By environmentally friendly processes production equipment and products we contribute to the protection of our environment To be able to reuse the TQMa6x it is produced i...

Страница 55: ...le SPI EEPROM Electrically Erasable Programmable Read only Memory EIA Electronic Industries Alliance EIM External Interface Module EMC Electro Magnetic Compatibility eMMC embedded Multi Media Card EPI...

Страница 56: ...RAM Random Access Memory REACH Registration Evaluation Authorisation and restriction of Chemicals RF Radio Frequency RGB Red Green Blue RGMII Reduced Gigabit Media Independent Interface RMII Reduced M...

Страница 57: ...6 2015 NXP 8 IMX6SDLCE Chip Errata for the i MX6 Solo DualLite Revision 5 12 2014 NXP 9 IMX6DQ6SDLHDG Hardware Development Guide for i MX 6Quad 6Dual 6DualLite 6Solo Revision 1 06 2013 NXP 10 MMPF0100...

Страница 58: ...TQ Systems GmbH M hlstra e 2 l Gut Delling l 82229 Seefeld Info TQ Group TQ Group...

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