TXZ Family
Flash Memory
2018-06-05
30 / 120
Rev. 2.0
Code Flash
3.1.1. Command Sequence
3.1.1.1. List of Command Sequence
This section shows addresses and data of the bus write cycle in each command of code flash.
Except the 5
th
bus cycle of ID-Read command, all cycles are “bus write cycles”. A bus write cycle is performed by a
32-bit (1 word) data transfer instruction. “Table 3.2
Flash memory access using the internal CPU (code flash)”
only shows the lower 8 bits data.
For details of addresses, refer to “Table 3.3Address bit configuration in the bus write cycle (Code flash)”. Use the
values in the table below to Addr[11:4] where “Command” is inputted.
Note: Each command address is set to a flash area (mirror).
Table 3.2 Flash memory access using the internal CPU (code flash)
Sequence
Command
1
st
bus
cycle
2
nd
bus
cycle
3
rd
bus
cycle
4
th
bus
cycle
5
th
bus
cycle
6
th
bus
cycle
7
th
bus
cycle
Address
Address
Address
Address
Address
Address
Address
Data
Data
Data
Data
Data
Data
Data
Read/Reset
0xYYYYXXXX
-
-
-
-
-
-
0xF0
-
-
-
-
-
-
ID-Read
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
IA
0xYYYYXXXX
-
-
0xAA
0x55
0x90
0x00
ID
-
-
Automatic
programming
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
PA
PA
PA
PA
0xAA
0x55
0xA0
PD0
PD1
PD2
PD3
Automatic page
erasing
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
0xYYYYX55X
0xYYYYXAAX
PGA
-
0xAA
0x55
0x80
0xAA
0x55
0x40
-
Automatic block
erasing
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
0xYYYYX55X
0xYYYYXAAX
BA
-
0xAA
0x55
0x80
0xAA
0x55
0x30
-
Automatic area
erasing
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
0xYYYYX55X
0xYYYYXAAX
AA
-
0xAA
0x55
0x80
0xAA
0x55
0x20
-
Automatic code
area erasing
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
-
0xAA
0x55
0x80
0xAA
0x55
0x11
-
Automatic chip
erasing
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
-
0xAA
0x55
0x80
0xAA
0x55
0x10
-
Automatic
protect bit
programming
0xYYYYX55X
0xYYYYXAAX
0xYYYYX55X
PBA
-
-
-
0xAA
0x55
0x9A
0x9A
-
-
-