Toshiba TMPM3V4, Руководство пользователя

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12.12 Interrupt/Error Generation Timing
12.12.1 Receive Interrupts
Figure 12-13 shows the data flow of receive operation and the route of read.
Receive FIFO First stage
second stage
Third stage
Fourth stage
Receive buffer
Receive shift register
If the receive buffer is emp t y,
the data is moved.
If the RX FIFO is not full,
the data is moved.
(1)Reading in the single buffer configuration :
An interrupt is generated after receiving all bits.
(2)Reading in the dou b le buffer configuration :
An interrupt is generated when the data is moved to
the receive buffer.
(3)Reading in use the FIFO :
An interrupt is generated
When the data is moved to the FIFO
or when reading the FIFO.
R XDx
Figure 12-13 Receive Buffer/FIFO Configuration Diagram
12.12.1.1 Single Buffer / Double Buffer
Receive interrupts are generated at the time depends on the transfer mode and the buffer configura-
tions, which are given as follows.
Table 12-7 Receive Interrupt Conditions in use of Single Buffer / Double Buffer
Buffer
Configurations
UART modes IO interface modes
Single Buffer −
Immediately after the raising / falling edge of the last SCLKx pin
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
Double Buffer
A receive interrupt occurs when data is trans-
ferred from the receive shift register to the re-
ceive buffter.Specific timings are :
・
If data does not exist in the receive buffer,
a receive interrupt occurs in the vicinity of the
center of the 1st stop bit.
・
If data exists in both the receive shift regis-
ter and the receive buffer, a receive interrupt
occurs when the buffer is read.
A receive interrupt occurs when data is transferred from the receive shift regis-
ter to the receive buffer.Specific timings are:
・
If data does not exit int the receive buffer, a receive interrupt occurs
immedi-ately after on rising/falling edge of SCLK x pin of the last bit.
(The setting of rising edge or falling edge is specified with SCxCR<SCLKS>.)
・
If data exists in both the receive shift register and the receive buffer, a re-
ceive interrupt occurs when the buffer is read.
Note: Interrupts are not generated when an over-run error is occurred.
12.12.1.2 FIFO
When the FIFO is used, a receive interrupt occurs on depending on the timing described in Table 12-8
and the condition specified with SCxRFC<RFIS>.
Table 12-8 Receive Interrupt Conditions in use of FIFO
SCxRFC<RFIS> Interrupt conditions Interrupt generation timing
"0"
When FIFO fill level (SCxRST<RLVL[2:0]>) = Receive
FIFO fill level to generate receive interrupt <RIL[1:0]>
・
When transfer a received data from receive buffer to receive FIFO
・
When read a receive data from receive FIFO
"1"
When FIFO fill level (SCxRST<RLVL[2:0]>) ≥ Receive
FIFO fill level to generate receive interrupt <RIL[1:0]>
・
When read a receive data from receive FIFO
TMPM3V6/M3V4
Page 251
2019-02-06