Toshiba TCK401G, Справочное руководство

Страница: 11 / 15

RD002-RGUIDE-01
2018-03-07
Rev. 1
11 / 15
© 2018
Toshiba Electronic Devices & Storage Corporation
Figure 4.1 shows the timing chart of the V
CT
and V
GATE
pins. The V
GATE
ON time (t
ON
) shown in
the AC Characteristics table in the datasheet is the time required from the 50% point of V
CT
rise
edge when the V
GATE
voltage reaches V
IN
+1V. The slew rate control circuit maintains the slope
of the V
GATE
output. Therefore, the higher the V
IN
voltage, the longer the V
GATE
ON time (t
ON
).
The V
GATE
OFF time (t
OFF
) shown in the AC Characteristics table in the datasheet is the time
required from the 50% point of V
CT
fall edge when the V
GATE
voltage reaches 0.5V.

V
SRC
pin
In the circuit which the TCK401G drives two MOSFETs, the V
SRC
pin has internal MOSFET and
make short-circuits to the V
GATE
output through the source of the MOSFETs when the TCK401G
turns off. The V
SRC
pin may be left open if the MOSFET gate-source voltage (V
GS
) has enough
margin. In cases of the TCK401G driving only one MOSFET, the V
SRC
pin may also be left open if
the MOSFET gate-source voltage (V
GS
) has enough margin. It is recommended to connect V
SRC
to V
OUT
if V
GS
does not have an enough margin.

DIS pin
Connect the DIS pin to V
OUT
if automatic output discharge is necessary when the TCK401G
turns off. Otherwise, the DIS pin may be left open.

Overvoltage protection “off” time (t
OVP
)
Overvoltage lockout (OVLO) trips to turn off V
GATE
when V
IN
exceeds the maximum value of
V
in_opr
. The OVLO “off” time (t
OVP
) is equal to the V
GATE
OFF time (t
OFF
).
Figure 4.2 T
OVP
timing chart