[6] Handling Guide
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3.3.13 Meta-Stable
Characteristics
When the setup time or hold-time of a flip-flop is not adhered to the device’s output response is
uncertain. This phenomenon is called meta-stability.
The diagram shown above describes a meta-stable state which can generate a glitch or increase the
propagation delay time. If the asynchronous signal is an input to a flip-flop which is clocked by the
internal clock of a synchronous system, the meta-stable state is unavoidable.
Therefore, in order to avoid this problem, it is recommended that the timing requirements specified
in the data sheet be observed. When a synchronous signal is used, care must be taken with the output
signal.
Figure 3.8 shows an example of how to solve this problem. In this case, if the difference in phase
between CK1 and CK2 is the same as the tpd (output clock) of the first stage flip-flop, care must be
taken.
Note:
If CK1 and CK2 cannot be used together, the synchronous clock signal used for CK1 should be phase-
shitted and applied as the clock for Second stage flip-flop (CK2) (i.e.
2
CK
=
CK1)
Figure 3.8 Solving the Meta-stable Problem
t
s
>
min
Asynchronous Data
Clock
Output
t
h
>
min
t
pd
<
=
max
t
s
??
t
h
??
t
pd
??
Asynchronous Input
Clock
Synchronous Output
D
Q
CK
D
Q
CK1
D
Q
CK2
Synchronous Output
Asynchronous Input
Clock
