Toshiba BDX2500KU, Руководство по обслуживанию

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5-2
IC5201 NT5CB64M16AP/NT5CB128M8AN/NT5CB256M4AN - 2
Input / Output Functional description
Symbol Type
Active Low Asynchronous Reset:
Reset is avtive when RESET# is LOW, and
inactive when RESET# is HIGH. RESET# must be HIGH during normal operation.
RESET# is a CMOS rail to rail signal wigh DC high and low at 80% and 20% of VDD,
I,e, 1.20V for DC high and 0.30V.
NC
No Connect:
No internal electrical connection is present.
VDDQ Supply
DQ Power Supply:
1.5V ± 0.075V
VDD Supply
Power Supply:
1.5V ± 0.075V
VSSQ Supply
DQ Ground
VSS Supply
Ground
VREFCA Supply
Reference voltage for CA
VREFDQ Supply
Reference voltage for DQ
ZQ Supply
Reference pin for ZQ collbration.
Note: Input only pins (BA0-BA2,A0-A13,RAS,CAS,WE,CS,CKE,ODT, and RESET) do not supply termination.
DDR3 SDRAM Addressing
NT5CB256M4AN NT5CU128M8AN NT5CB64M16AP
# of Bank
8 8 8
Bank Address
BA0 - BA2 BA0 - BA2 BA0 -BA2
Auto precharge
A10 / AP A10 / AP A10 / AP
BL switch on the fly
A12 / BC A12 / BC A12 / BC
Row Address
A0 - A13 A0 - A13 A0 - A12
Column Address
A0 - A9,A11 A0 - A9 A0 - A9
Page size
1KB 1KB 2KB
Note:
Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command
is registered. Page size per bank, calculated as follows:
Page size = 2 COLBITS * ORG / 8
COLBITS = the number of column address bits
ORT = the number of I/O (DQ) bits
Configuration
Function
Input RESET