Toshiba 29VH27E, Руководство по обслуживанию

Страница: 70 / 171

9
19 N.C. Not connected
20 N.C. Not connected
21 V
DD3
+ 5 V digital supply
22 N.C. Not connected
23 V
REF
+ 3 V reference voltage input
24 N.C. Not connected
25 V
DD4
+ 5 V digital supply
26 A8 External DRAM-address
27 A7 External DRAM-address
28 A6 External DRAM-address
29 A5 External DRAM-address
30 A4 External DRAM-address
31 A3 External DRAM-address
32 A2 External DRAM-address
33 A1 External DRAM-address
34 A0 External DRAM-address
35 A9 External DRAM-address
36 A10 External DRAM-address
37 A11 External DRAM-address
38 RASQ Row address strobe (DRAM)
39 WEQ Write enable (DRAM)
40 D1 External DRAM-data
41 D0 External DRAM-data
42 D2 External DRAM-data
43 D3 External DRAM-data
44 V
SS4
0 V digital supply
45 CASQ Column address strobe
46 N.C. Not connected
47 N.C. Not connected
48 N.C. Not connected
49 V
SS3
0 V digital supply
50 N.C. Not connected
51 N.C. Not connected
52 N.C. Not connected
53 N.C. Not connected
54 N.C. Not connected
55 V
SS2
0 V digital supply
56 V
BB
Substrate bias voltage N.C.* (depends on version)
57 N.C. Not connected
58 V SSA2 Analog ground
59 RGB-GND RGB-ground
60 V
SS1
0 V digital supply
61 R Analog red display output
62 G Analog green display output
63 B Analog blue display output
64 BLAN Blanking signal open drain output
65 CORQ Contrast reduction open drain output
66 SCL Bi-directional I
2
C Bus clock port
67 SDA Bi-directional I
2
C Bus data port
68 I
2
CEN I
2
C Bus enable
14.5.DRAM 4MX4
14.5.1.General Description
The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits
organized in a x4 con-figuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12
bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the
latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are “don’t care”). READ and
WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates READ mode, while a
logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling
edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior
to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken
LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z regardless of the state of
OE#. During LATE WRITE or READ-MODIFY -WRITE cycles, OE# must be taken HIGH to disable the