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EX-300-96122 User's Manual
Chipset Features Setup
DRAM Settings
The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered if
data is being lost. Such a scenario might well occur if your system had mixed speed
DRAM chips installed so that greater delays may be required to preserve the integrity of
the data held in the slower memory chips.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing.
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle
SDRAM RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used
when DRAM is written to, read from, or refreshed. Fast gives faster performance; and
Slow gives more stable performance. This field applies only when synchronous DRAM is
installed in the system.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain data. Fast
gives faster performance; and Slow givesmore stable performance. This field applies only
when synchronous DRAM is installed in the system.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting
in better system performance. However, if any program writes to this memory area, a
system error may result.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result.
CPU latency Timer
When enabled this item, the CPU cycle will only be deferred after it has been held in a
"Snoop Stall" for 31 clocks and another ADS# has arrived. When disabled, the CPU cycle
will be deferred immediatedly after the GMCH receives another ADS#.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1
AGP Graphics Aperture Size
This fielf determines the effective size of the Graphic Aperture used for a particular GMCH
configuration. It can be updated by the GMCH-specific BIOS configuration sequence
before the PCI standard bus enumeration sequence takes place. If it is not updated then
a default value will select an aperture of maximum size.
Display Cache Frequency
You can use this item to select the frequency of the display cache.
System Memory Frequency
You can use this item to select the operating frequency for the main system.
On-Chip Video Window Size
Select the on-chip video window size for VGA drives use.
