Preliminary
THCV245A_Rev.0.90_E
Copyright©2020 THine Electronics, Inc.
THine Electronics, Inc.
Security C
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6.3
MIPI input setting
Setting of MIPI input can be configurable by 2-wire access to internal register.
Lane0 of MIPI input must always be used regardless of configuration as an obligation.
Table 1.
MIPI input setting
Addr(h)
Bits
Register
w idth
R/W
Description
Default
0x1025
[0]
R_RX_PN_SW
1
R/W
MIPI P/N sw ap
1'h0
0x1026
[7:6]
R_RX_LANE_SEL0
2
R/W
MIPI Data Lane RX0P/RX0N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX0P/RX0N input
The same setting as R_RX_LANE_SEL1/2/3 is prohibited.
2'h0
0x1026
[5:4]
R_RX_LANE_SEL1
2
R/W
MIPI Data Lane RX1P/RX1N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX1P/RX1N input
The same setting as R_RX_LANE_SEL0/2/3 is prohibited.
2'h1
0x1026
[3:2]
R_RX_LANE_SEL2
2
R/W
MIPI Data Lane RX2P/RX2N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX2P/RX2N input
The same setting as R_RX_LANE_SEL0/1/3 is prohibited.
2'h2
0x1026
[1:0]
R_RX_LANE_SEL3
2
R/W
MIPI Data Lane RX3P/RX3N pin input mapping/sw ap select
MIPI standard format lane# assignment used on RX3P/RX3N input
The same setting as R_RX_LANE_SEL0/1/2 is prohibited.
2'h3
0x102C
[0]
R_RX_CLKLANE_EN
1
R/W
MIPI Clock Lane Enable
0:Disable
1:Enable
1'h0
0x102D
[4]
R_RX_DATALANE_EN
1
R/W
MIPI Data Lane Enable
0:Disable
1:Enable, follow ing R_RX_LANE_SEL_EN
1'h0
0x102D
[1:0]
R_RX_LANE_SEL_EN
2
R/W
MIPI Valid Data Lane number select
00:1Lane (lane0 Enable)
01,10:2Lane (lane<1:0> Enable)
11:4Lane (lane<3:0> Enable)
2'h3
