THine THCV245 A, Руководство пользователя

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Preliminary
THCV245A_Rev.0.90_E
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6.15 V-by-One® HS HSYNC generation
Setting of V-by-One® HS HSYNC output is configurable by 2-wire access on internal register.
Internally generated HSYNC in Vertical active period (R_HS_MODE=10/11) follows Figure 9.
Internally generated HSYNC in Vertical blanking period (R_HS_VB_EN=10/11) follows Figure 10.
Table 26. V-by-One® HS output HSYNC setting
Figure 9. Internally generated HSYNC in Vertical active period
Addr(h) Bits Register w idth R/W Description Default
0x1002 [1:0] R_LS_LE_SYNCEN 2 R/W
V-by-One® HS Hsync generation Enable at MIPI LS/LE
(active only w hen R_HS_MODE=00, 01)
00:Hsync pulse at both LS and LE (THCV242-Q default)
01:Hsync pulse at LS only
10:Hsync pulse at LE only
11:no Hsync pulse at LS nor LE
2'h0
0x1004 [0] R_HSYNC_POL 1 R/W
V-by-One® HS Hsync polarity
0:High pulse (High active) (THCV242-Q default)
1:Low pulse (Low active)
1'h0
0x1009 [1:0] R_HS_MODE 2 R/W
V-by-One® HS HSYNC output timing mode
00, 01:MIPI LS/LE timing direct use mode (THCV242-Q def ault)
10:internally generated timing mode1
11:internally generated timing mode2
2'h0
0x100A [4:0] R_VACT_LINE[12:8] 5 R/W V-by-One® HS Vactive line skip number MSB 5'h00
0x100B [7:0] R_VACT_LINE[7:0] 8 R/W V-by-One® HS Vactive line skip number LSB 8'h00
0x100C [1:0] R_HS_VB_EN 2 R/W
V-by-One® HS HSYNC output in vertical blanking period setting
00, 01:no HSYNC output in Vblank
10:HSYNC output in Vblank, starting from FE
11:HSYNC output in Vblank, starting from FS, skipping Vactive
2'h0
0x100D [7:0] R_HS_VB_NUM 8 R/W V-by-One® HS HSYNC output number in vertical blanking period 8'h00
V-by-One® HS
PCLK
MIPI long packet MIPI long packet
V-by-One® HS
DE (Data Enable)
Internally
generated
HSYNC mode1
Internally
generated
HSYNC mode2
R_HS_MODE=10 ( For example, R_HSYNC_POL=0 )
R_HS_MODE=11 ( For example, R_HSYNC_POL=0 )
2 x PCLK 2 x PCLK 2 x PCLK