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QFLG:UTO
QUPRD
32
QUTMR
32
QEPCTL:UTE
UTIME
SYSCLKOUT
UTOUT
8
eQEP Interrupt Structure
Clr
Set
Latch
QFRC:PCE
PCE
QCLR:PCE
QFLG:PCE
QEINT:PCE
QCLR:UTO
QFRC:UTO
QEINT:UTO
set
Latch
clr
UTO
QFLG:UTO
0
1
0
Pulse
generator
when
input=1
QFLG:INT
Latch
Set
Clr
QCLR:INT
EQEPxINT
9
eQEP Registers
eQEP Interrupt Structure
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Figure 19. eQEP Unit Time Base
shows how the interrupt mechanism works in the EQEP module.
Figure 20. EQEP Interrupt Generation
Eleven interrupt events (PCE, PHE, QDC, WTO, PCU, PCO, PCR, PCM, SEL, IEL and UTO) can be
generated. The interrupt control register (QEINT) is used to enable/disable individual interrupt event
sources. The interrupt flag register (QFLG) indicates if any interrupt event has been latched and contains
the global interrupt flag bit (INT). An interrupt pulse is generated only to the PIE if any of the interrupt
events is enabled, the flag bit is 1 and the INT flag bit is 0. The interrupt service routine will need to clear
the global interrupt flag bit and the serviced event, via the interrupt clear register (QCLR), before any other
interrupt pulses are generated. You can force an interrupt event by way of the interrupt force register
(QFRC), which is useful for test purposes.
28
Enhanced QEP (eQEP) Module
SPRUG05A – August 2008 – Revised December 2008