Texas Instruments XTR108, Руководство пользователя

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I
Z_FINE
=
8 R
VI
5 V
REF
64
N
12
V
Z_FINE
=
80
V
REF
64
N
12
I
Z_COARSE
=
8 R
VI
5 V
REF
4
N
13
V
Z_COARSE
=
80
V
REF
4
N
13
I
Z_PROGRAM
=
8 R
VI
175 V
REF
V
Z_PROGRAM
=
8
3.5 V
REF
50*A
PGA
*I
REF
*(RTD
MIN
- R
Z
)
R
VI
I
ZERO
= I
OUT_MIN
-
V
ZERO
= V
Z_PROGRAM
+ V
Z_COARSE
+ V
Z_FINE
Software Overview
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28 SBOU123A – March 2012 – Revised September 2016
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XTR108EVM-USB Evaluation Board and Software Tutorial
5.1.2 PGA
The differential input voltage created by the current sources I
REF1
and I
REF2
flowing through the RTD and R
Z
resistances is applied to the input pins of a programmable-gain instrumentation amplifier (PGA). The PGA
has seven voltage-gain settings in binary steps from 6.25 V/V to 400 V/V. The input common-mode range
of the PGA is 0.2 V to 3.5 V above the I
RET
potential.
For common applications that require a 4-mA to 20-mA transmission, the PGA output voltage range
should be set to V
ZERO
= 0.5 V and V
FS
= 2.5 V. Connecting an external voltage-to-current resistor (R
VI
=
6.34 k Ω ) between pin 9 (V
O
) and pin 10 (I
IN
) converts this voltage to a current that passes to the 50-A/A
fixed-gain output current amplifier which produces a 4-mA to 20-mA output. In this mode, the PGA voltage
gain converts to an overall transconductance in the range of 50 mA/V to 3200 mA/V (approximately).
Table 20 shows the gain to transconductance relationship. For voltage-output applications, the PGA can
be set for rail-to-rail output (for example, V
ZERO
= 0.5 V and V
FS
= 4.5 V). The PGA section of the block
diagram shows the PGA voltage gain setting in V/V.
Table 20. PGA Gain, Loop Transconductance, and Input Full-Scale Differential Voltage
Voltage Gain
(V/V)
Output Transconductance
(mA/V)
Full-Scale Differential V
IN
(mV)
6.25 49 320
12.5 99 160
25 197 80
50 394 40
100 789 20
200 1577 10
400 3155 5
5.1.3 I_ZERO DAC
The zero-output level of the XTR108 input PGA is controlled by two DACs (coarse and fine). These digital-
to-analog converters (DACs) compensate for the initial offset at the PGA input as a result of sensor and
resistor mismatches as well as sensor non-idealities. Both the coarse and fine DAC are bidirectional
(positive or negative) and allow the output level to be set above or below a preset pedestal. The equations
that define the output of these DACs are given in
Table 21 . Note that the external resistor R
VI
(voltage-to-
current conversion resistor) is used to convert the DAC reference voltage (V
REF
) into a current. The I
ZERO
DAC section of the block diagram shows the value of the coarse and fine zero-scale output DACs.
(1)
N
13
and N
12
are the decimal values of registers 13 and 12, respectively.
Table 21. Equations for Calculating Zero Output
(1)
DAC Output
Voltage Referred to V
O
Pin
with Respect to I
RET
Current Referred to I
OUT
Pin
Overall
Program
Coarse DAC
Fine DAC