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JT
AG Connector
Logic
Analyzer Connector
UART PC Connection
1
Parts not used
1
R9
10K
R10
10K
R5
10K
R7
10K
R8
10K
R4
10K
R6
0
1
2
3
4
5
6
7
8
9
10
1
1
12
13
14
J1
TP12
TP15
TP14
TP1
1
1
2
3
4
5
6
7
8
9
10
1
1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
J35
TP1
C8
0.1uF
1
2
3
4
5
6
7
8
9
10
11
J4
TP2
C7
0.1uF
C5
0.1uF
TP3
C10
0.1uF
1
EN
2
C1+
3
V+
4
C1-
5
C2+
6
C2-
7
V
-
8
R1IN
9
R1OUT
10
INV
ALID
1
1
T1IN
12
FORCEON
13
T1OUT
14
GND
15
VCC
16
FORCEOFF
U4
SN75C3221DBR
C9
0.1uF
J16
J17
+3_3V
[1,2,4,5,6,9]
TCK/TCAP/SYNC/PWM0
[1,2,4]
TDO/SCI_TX0/F
AUL
T0
[1,2,4,5]
+3_3V
[1,2,4,5,6,9]
TDI/SCI_RX0/F
AUL
T1
[1,2,4,5]
+3_3V
[1,2,4,5,6,9]
TMS
[1,2]
DPWM3B
[1,2,7]
DPWM3A
[1,2,7]
DPWM2A
[1,2,7]
DPWM1B
[1,2,7]
DPWM0B
[1,2,7]
DPWM0A
[1,2,7]
DPWM2B
[1,2,7]
DPWM1A
[1,2,7]
PMBUS_DA
T
A
[1,2,6]
PMBUS_CLK
[1,2,6]
/RESET
[1,2]
PWM0/SYNC/TCAP/ADC_EXT/ADC_EXT
[1,2,4]
F
AUL
T2
[1,2]
PMBUS_ALER
T [1,2,6]
PMBUS_CTRL
[1,2,6]
+3_3V
[1,2,4,5,6,9]
DGND
DGND
DGND
DGND
TDO/SCI_TX0/F
AUL
T0
[1,2,4,5]
TDI/SCI_RX0/F
AUL
T1
[1,2,4,5]
Schematics
Figure 5. UCD3138OL40EVM-032 Schematics (UART and JTAG) 5 of 9
8
Using the UCD3138OL40EVM-032
SLUUA80 – January 2013
Copyright © 2013, Texas Instruments Incorporated