+5V
INPUT
16V
OUTPUT
0V
0V
10%
90%
10%
90%
(a)
90%
90%
10%
90%
(b)
INPUT
OUTPUT
10%
t
d1
t
d2
t
f
t
f
t
d1
t
f
t
f
t
d2
Performance Data, Test Verfication Waveforms, and Typical Characteristic Curves
13
SLVUB27 – March 2017
Copyright © 2017, Texas Instruments Incorporated
UCC27423-4-5-Q1 EVM User’s Guide
4.3.2
Power-Up Procedure
To power the EVM, follow these steps:
Step 1.
Power the board with 5 V through VDD, and set the current limit below 1 A.
Step 2.
Place a 5-V power supply between FET_VDD and GND, and set the current limit below 1 A.
Step 3.
Connect the signal generator outputs to INA and INB and adjust the signal generator to
produce a signal between 2.75 V and 5.5 V at desired frequency and duty cycle.
Step 4.
Remove the jumpers on J7 and J8.
Step 5.
Use FET_OUTA and FET_OUTB with a scope to capture desired waveforms.
5
Performance Data, Test Verfication Waveforms, and Typical Characteristic Curves
5.1
Propagation Delay, Rise and Fall Times
shows the propagation delay, rise and fall times as measured on the EVM.
also
shows the switching waveforms for inverting driver (a) and noninverting driver (b).
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 14. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
5.2
Propagation Delay, Rise, and Fall Times Results
The load capacitance testing condition is 1.8 nF, VDD = 5 V, and the driver signal voltage is set to 5 V
with f = 300 kHz, connected to INA and INB.
lists the EVM test results.
Table 6. EVM Test Results
Part Number
Delay Time, IN Rising
(IN to OUT)
Delay Time, IN Falling
(IN to OUT)
Rise Time
Fall Time
UCC27423-Q1
27 ns
49 ns
21 ns
16 ns
UCC27424-Q1
40 ns
34 ns
19 ns
17 ns
UCC27425-Q1
41 ns
51 ns
17 ns
16 ns