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Connector and Test Point Descriptions
Copyright © 2012, Texas Instruments Incorporated
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Connector and Test Point Descriptions
4.1 Connector Descriptions
4.1.1
Boot Pins
JP6, JP7, and JP8 are used to select the boot pin configuration for proper booting of the device.
shows the possible boot options.
Table 1. Boot Configuration
State
Boot0
Boot1
Boot2
1
JP6(1-2)
JP7(1-2)
JP8(1-2)
0
JP6(3-2)
JP7(3-2)
JP8(3-2)
4.1.2
Backup Battery
JP9 is used for the backup battery connection. The user can use the onboard 0.8-F, 3.3-V capacitor by
shorting JP9-1 and JP9-2.
4.1.3
VBAT and VSYS
Pack+/– (JP2) is the main source input to the PMIC. See
for the minimum and maximum levels
that can be applied to this pin. Use JP12 for ground; the power supply V+ is JP2 (1) and V– to JP2 (2).
Table 2. VBAT Minimum and Maximum Levels
VBAT
Minimum (V)
Typical (V)
Maximum (V)
2.7
3.6
5.5
VSYS (JP1) is the main input source to the device.
lists the minimum and maximum levels that
can be applied to these pins.
Table 3. VSYS Minimum and Maximum Levels
VSYS
Minimum (V)
Typical (V)
Maximum (V)
2.7
3.6
5.5
VBUS (JP4) plug insertion is one of the power up events for the device; VBUS is set to 5 V. It is not
mandatory to plug in VBUS for power up of the PMIC.
4.1.4
SMPS
There are five SMPSs on the TWL6032 device. SMSPs can be loaded by connecting the load on
connectors JP13 and J3. Special consideration must be given to force and sense while loading on SMPS1
(JP13).
lists the maximum loads of the SMPSs.
Table 4. SMPS Loads
Connector
Label
Maximum Load
JP9(1-4)
SMPS1
5 A
J12(6-1)
SMPS2
2.2 A
J12(8-1)
SMSP3
1.1 A
J12(10-1)
SMSP4
1.1 A
J12(12-1)
SMSP5
1.1 A
SWCU105 – October 2012
TWL6032 Evaluation Module (EVM) User’s Guide
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