Texas Instruments TVP5154A, Быстрый старт

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// Example C Code for WSS/CGMS NTSC Sliced Data Read
// Load C-RAM
// Configure Line Mode Registers
byte Status;
byte WSSData[3];
I2CReadBuffer(TVP5154A,0xC6,&Status,1); //read 1 byte(status)from register C6h
if ((Status & 0x20) == 1)
{
I2CReadBuffer(TVP5154A,0x94,&WSSData[0],3); // if WSS/CGMS bit set,
// read the 3 WSS/CGMS bytes
// at WSS/CGMS data registers 94h–96h.
I2CWriteByte(TVP5154A,0xC6,0x20); // clear WSS/CGMS available status bit
}
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Sliced Data Retrieval
4 Sliced Data Retrieval
The TVP5154A provides dedicated I
2
C registers (see Table 4 ) for the retrieval of sliced data. Due to
higher bandwidth requirements, teletext data is stored in a 512-byte FIFO. With all other data services,
sliced data can be automatically sent to the dedicated registers or to the FIFO depending on the line mode
setup. The WSS/CGMS example in
Figure 3 results in WSS/CGMS data being routed to the dedicated
WSS/CGMS data registers.
Table 4. Dedicated VDP Data Registers
Register Name I
2
C Address
VDP Closed Caption Data (field 1) 90h - 91h
VDP Closed Caption Data (field 2) 92h - 93h
VDP WSS/CGMS Data (field 1) 94h - 96h
VDP WSS/CGMS Data (field 2) 97h - 99h
VDP VPS (PAL) /Gemstar 2x (NTSC) 9Ah - A6h
Data
VDP VITC Data A7h - AFh
The internal 512-byte FIFO is used primarily for high-bandwidth teletext acquisition but can also be used
for capture of the other data services if enable in the Line Mode register. A header containing information
about the sliced data precedes all sliced data that is routed to the FIFO. The FIFO can be directly
accessed by the host at I
2
C address B0h. Bit 0 of the FIFO output control register (CDh) must be set to a
logic1 to enable host access to the FIFO.
5 Managing Data Retrieval
The VDP Status Registers (C6h) can be used to determine if sliced data is available. Unmasked data
available bits for the supported data services are available in this register.
VDP Status Register
Address C6h
7 6 5 4 3 2 1 0
FIFO full error FIFO empty TTX available CC field 1 CC field 2 WSS/CGMS VPS/Gemstar VITC available
available available available 2x available
A logic 1 indicates that sliced data is available. Once set, these bits need to be cleared after data retrieval. Writing a 1 to the appropriate
bit(s) in this register clears the status bit.
Figure 4 shows an example WSS/CGMS data retrieval.
Figure 4. Example WSS/CGMS Data Retrieval
7 SLEA104 – July 2010 TVP5154A VBI Quick Start
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