Adapter Reference
6.
Start evaluating the TSW4200 Demonstration Kit by configuring the FPGA to transmit data to the DAC
EVM and receive data from the ADC EVM.
4
Adapter Reference
Visit
for more information on the following adapter board options.
•
FMC-ADC-Adapter,
http://focus.ti.com/docs/toolsw/folders/print/fmc-adc-adapter.html
•
FMC-DAC-Adapter,
http://focus.ti.com/docs/toolsw/folders/print/fmc-dac-adapter.html
•
HSMC-ADC-Bridge,
http://focus.ti.com/docs/toolsw/folders/print/hsmc-adc-bridge.html
5
Notes on Interfacing with Xilinx 7-Series FPGA
The connections between the TSW4200 kit and FMC (HPC or LPC) connectors on a Xilinx 7-Series FPGA
EVM spread the input/output buses of the ADC/DAC over two IO-banks. This makes it necessary to use
the BUFMR clock buffer in the FPGA in order to clock data in multiple clock regions.
For detailed information about this clock buffer, refer to the 7-Series FPGA Clocking Resources User
Guide (Xilinx UG472, Multi-Region Clocking). The use case Driving Multiple BUFRs (with Divide) and
BUFIO in particular, provides extensive details over the implementation.
In an actual end-user system implementation, ADC and DAC connections to the FPGA should utilize a
single FPGA IO-bank for a simpler approach.
For an ADC with serial LVDS output implementation, half of an IO-bank can handle all connections from
the ADC:
•
Connect the bit clock DCLK_p/n to a MRCC differential clock input.
•
Connect the frame clock FCLK_p/n to the neighbor SRCC differential clock input.
•
Connect all data inputs to normal differential inputs starting from the FCLK_p/n.
For a DAC with parallel LVDS input implementation, connections to the FPGA often use several data
buses, and an optimal connection can be made as:
•
Connect the clock coming from the DAC, from the VCXO, or other clocking device to a MRCC
differential input.
•
Connect the clock and data connections to the DAC in the same IO-bank and neighbor (above and
below) IO-banks.
7
SLWU071C – April 2010 – Revised November 2012
TSW4200 Demonstration Kit
Copyright © 2010–2012, Texas Instruments Incorporated