Texas Instruments TSW40RF8 Series, Руководство пользователя

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Optional Modes and Information
9 SLAU706A – January 2017 – Revised September 2017
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TSW40RF8x Evaluation Module
5.6 Alternative Configuration File Options
Table 1 and Table 2 describe the available pre-created configuration file options. Check the
TSW40RF8xEVM product page for updated configuration files if desired.
Table 1. Configuration File Name
File # File Name
1 2T2R_RevC_ConstInput_12xDec_18xInt_2949p12M_4915p2Gb.cfg
2 2T2R_RevC_ConstInput_8xDec_12xInt_2949p12M_7372p8Gb.cfg
3 2T2R_RevC_ConstInput_12xDec_24xInt_2949p12M_5898p2_2IQ_4915p2Gb.cfg
4 2T2R_RevC_ADC-BypassLMFS82820_18xInt_2949p12.cfg
5 2T2R_RevC_ADC-Bypass-82820_DAC-Int18x-8847p36M_TxClkOut-Div3.cfg
6 2T2R_RevC_ConstInput_12xDec_18xInt_2949p12M_4915p2Gb_TXClkOut-Div3.cfg
7 2T2R_RevC_ConstInput_12xDec_12xInt_2949p12M_5898p2_4915p2Gb.cfg
8 2T2R_RevC_ConstInput_6xDec_18xInt_2949p12M_4915p2Gb_2ndNyquist.cfg
9 2T2R_RevC_ConstInput_6xDec_12xInt_2949p12M_5898p2_4915p2Gb.cfg
10 2T2R_RevC_ConstInput_4xDec_12xInt_2949p12M_7372p8G.cfg
Table 2. Configuration File Description
File # TCVR
Mode
DAC
Clock
[MHz]
I/Q
Paths
Int NCO
[MHz]
Const
Input
Mode ADC
Clock
[MHz]
ADC
Clock
Source
Dec NCO
[MHz]
1 Yes 8847.36 1 18 1960 Yes DDC 2949.12 LMX 12 1890
2 No 8847.36 1 12 1960 Yes DDC 2949.12 LMX 8 1890
3 Yes 5898.24 2 24 1960 Yes DDC 2949.12 LMX 12 1890
4 No 8847.36 1 18 1960 Yes Bypass 2949.12 LMX - -
5 No 8847.36 1 18 1960 Yes Bypass 2949.12 DAC - -
6 Yes 8847.36 1 18 1960 Yes DDC 2949.12 DAC 12 1890
7 Yes 5898.24 1 12 1960 Yes DDC 2949.12 LMX 12 1890
8 Yes 8847.36 1 18 1960 Yes DDC 2949.12 LMX 6 1890
9 Yes 5898.24 1 12 1960 Yes DDC 2949.12 LMX 6 1890
10 No 8847.36 1 12 1960 Yes DDC 2949.12 LMX 4 1890
5.7 Manual Software Adjustment
In general, the GUI software operates similar to the individual GUIs of the DAC38RF8x EVM and the
ADC32RFxx EVM. It is possible to operate in a manual mode following the procedure of the RF DAC and
RF ADC respectively; however, there are a few minor differences.
5.7.1 RF DAC Set-Up Conditions
The DAC PLL reference frequency is derived from the LMK VCO divided down outputs. This is the only
way to provide this reference; there is no option for external PLL reference.
5.7.2 RF ADC Set-Up Conditions
• ADC SysRef is generated through the LMK device so its VCO must be set to the desired clocking
frequency.
• Clock divider for the FPGA is calculated based on SerDes rate of the DAC.