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8.7

Sideband Rejection

Basic Test Procedure

An iterative process is used to achieve the best performance.

•

Place a normal marker at the peak upper sideband, place a delta marker at the carrier signal, and note
the initial delta value.

•

Set initial DACA offset to 0 and DACB offset to 0.

•

Change DACA offset by 1000 steps and monitor the output performance change.

•

If performance gets better, then repeat the process with an additional 1000 steps. If the performance
gets worse or doesn't change, then change the offset in the other direction by 1000 steps.

•

Once the best performance remains basically unchanged, repeat the process on DACB offset with
1000 step changes.

•

Once optimized, go back to the A side and repeat the tuning process with a step size of 100.

•

Continue tuning. After each complete cycle, reduce the step size down (i.e., to 10, then to 1 if desired).

•

A performance greater that 70 dBc should be achievable.

Sideband rejection is determined by the two quadrature signals to the modulator being exactly 180
degrees out of phase and exactly the same amplitude. Amplitude and phase imbalance between the two
paths yield an unwanted lower sideband. The amplitude variation between the two paths can be
compensated for by adjusting the DAC fine gain controls or by adjusting the QMC gain controls if the
device is operating with the QMC on. The phase can be compensated by using the QMC phase
adjustment. Note this is only possible when the coarse mixer is not used in the f

DAC

/4 mode. Coarse

mixing in the f

DAC

/4 mode causes the relative phase information between I and Q paths to be mixed. In the

f

DAC

/2 mode there are no cross terms (terms are 0) and the relative phase information is maintained

between I and Q paths.

•

Place marker delta on the lower sideband

•

Turn on the QMC. Set the Gain of the QMC to 1024 for gain of 0 dB for I and Q paths. Other initial
settings may be needed depending on the state of the NCO gain and signal amplitude.

•

Change the phase of the QMC by small increments until the sideband is minimized.

•

Change the QMC A or B gains in increments of 1 until the sideband is minimized.

•

The overall performance should be greater than 60 dBc from the other sideband with amplitude and
phase corrections.

•

Re-optimized the dc-offset values as required to maintain carrier suppression performance as
specified.

Figure 22. DAC GUI With Typical Settings To Minimize LO and Sideband

26

TSW3003 Demonstration Kit

SLWU029D – October 2006 – Revised August 2007

Submit Documentation Feedback

           

Содержание TSW3003

Страница 1: ...est Mode 1 WCDMA Typical Performance With IF 153 6 MHz LO 2 14 GHz 17 12 ACPR Versus Output Power for 1Carrier WCDMA 18 13 ACPR Versus Output Power for 2 Carriers WCDMA 18 14 ACPR Versus Output Power for 3 Carriers WCDMA 19 15 ACPR Versus Output Power for 4 Carriers WCDMA 19 16 Optimum ACPR for 1 Carrier WCDMA 7 dB Pad 20 17 Optimum ACPR for 2 Carrier WCDMA 7 dB Pad 21 18 Optimum ACPR for 3 Carrie...

Страница 2: ...st 12 4 Input Output Connections 12 5 Demo Kit Typical Specifications 14 6 Frequency Designations 24 7 Bill of Materials 30 2 TSW3003 Demonstration Kit SLWU029D October 2006 Revised August 2007 Submit Documentation Feedback ...

Страница 3: ...The CDCM7005 requires a VCXO source to derive its output clock signals The VCXO is at reference designator U1 The frequency of the VCXO can be changed to operate the Demo Kit with different clocking schemes for different modulation standards or for specific customer requirements Denote which VCXO frequency is on the board so that the CDCM7005 part can be set up properly The following conventions a...

Страница 4: ...em block diagram in Figure 1 demonstrates where the TSW3003 Demo Kit fits in the overall transceiver The dash line box illustrates the components found on the TSW3003 Demo Kit board Figure 1 System Block Diagram The basic Demo Kit block diagram is shown in Figure 2 The shaded boxes illustrate the key Texas Instruments components found on the TSW3003 Demo Kit board Figure 2 Demo Kit Block Diagram T...

Страница 5: ...61 includes an integrated VCO and integer N PLL Different members of the TRF3761 family can be chosen for application specific VCO frequency ranges This section summarizes the installation procedures for the software required to operate the Demo Kit Once all of the software is loaded it is recommended to reboot the computer This software has been verified to be functional on Win2K and WinXP Execut...

Страница 6: ... brings up the interface seen in Figure 4 The default settings are correct for a VCXO of 491 52 MHz and a 10 MHz reference as on the TSW3003 The CDCM7005 GUI allows register settings to be saved and can be loaded back in afterwards This can be accomplished with the Save and Load Settings buttons near the right side of the GUI It is recommended that any unused output clocks be tri stated In this ca...

Страница 7: ...he VCXO frequency The OUT_MUX sets the divide ratios for the individual output clocks The OUTSEL determines whether the output clocks will be used as single ended CMOS or differential LVPECL With a 10 MHz reference oscillator the CDCM7005 settings are shown in Table 2 for a variety of common VCXO frequencies A calculator is included in the CDCM7005 GUI software to calculate the M and N values base...

Страница 8: ...ency and the R N A and B counter values to be programmed into the TRF3761 Hitting the Send button writes these values to the TRF3761 In default mode on a default board only the desired VCO frequency 2028 MHz to 2175 MHz needs to be changed For other VCO ranges a different member of the TRF3761 family needs to be selected and other parameters may need to be changed The Advanced Operation button wil...

Страница 9: ...he Demo Kit is not powered on or the USB cable is not connected an error message will be displayed instructing the user to correct the problem Once corrected hit the Read All button to read the default settings of the device Figure 7 DAC5687 GUI For normal operation the user needs only to select values and switches as desired The values are automatically sent to the device and read back to verify ...

Страница 10: ...iming relationship 2 s Comp When set input data is interpreted as 2 s complement When cleared input data is interpreted as offset binary Rev A Bus When cleared DA input data MSB to LSB order is DA 15 MSB and DA 0 LSB When set DA input data MSB to LSB order is reversed DA 15 LSB and DA 0 MSB Rev B Bus When cleared DB input data MSB to LSB order is DB 15 MSB and DB 0 LSB When set DB input data MSB t...

Страница 11: ... on the selected sync source the FIFO input and output pointers are initialized See the DAC5687 data sheet for source description DAC Coarse Gain Sets coarse gain of DAC A B full scale current Range is 0 to 15 See the DAC5687 data sheet for full scale gain equation DAC Fine Gain Sets fine gain of DAC A B full scale current Range is 128 to127 See the DAC5687 data sheet for full scale gain equation ...

Страница 12: ...Connect J31 20 CDC_PD Low active power down of CDCM7005 3 3 V Pin 20 21 J31 23 PD_OUTBUF Power down output buffer of TRF3761 GND Pin 22 23 J31 26 CHIP_EN Enable TRF3761 chip 3 3 V Pin 26 27 J31 29 RESET Low active reset of DAC5687 3 3 V Pin 29 30 J31 32 PLLLCK_EN Low active PLLLOCK output buffer GND Pin 31 32 J31 35 1 No Connect 1 VCXO does not have Output Enable control The input and output conne...

Страница 13: ...et up for general testing of the TSW3003 Demo Kit is shown in Figure 8 Figure 8 Test System Block Diagram The following is a list of the test equipment required for testing the TSW3003 Demo Kit Equivalent models may be used for certain applications but may produce different results due to limitations within the instrument Dual Power Supply Any with current readout capability or use the supplied 6V...

Страница 14: ...fset to that value The test specifications are outlined in Table 5 Table 5 Demo Kit Typical Specifications MIN MAX UNITS CURRENT 6 V 1 5 A CW TESTS Carrier suppression 30 dBc Sideband rejection 25 dBc Spurious Output 2nd harmonic 45 dBc Aliased LSB pos 40 dBc Output clock 40 dBc Aliased USB 15 dBc Aliased USB neg 8 dBc WCDMA ACPR Channel power 14 dBm ACPR Low 76 dBc ACPR High 76 dBc TSW3003 Demons...

Страница 15: ...er 11 85 dBm Adjacent Channel Bandwidth 3 84 MHz Lower 76 67 dB Spacing 5 MHz Upper 76 59 dB Alternate Channel Bandwidth 3 84 MHz Lower 77 96 dB Spacing 10 MHz Upper 77 75 dB POS 17 512 dBm Demo Kit Test Configuration Figure 9 Single Carrier Test Mode 1 WCDMA Typical Performance With IF 30 72 MHz LO 2 14 GHz SLWU029D October 2006 Revised August 2007 TSW3003 Demonstration Kit 15 Submit Documentatio...

Страница 16: ... 16 46 dBm Ref Ch2 88 87 dBm Ch3 16 56 dBm Total 13 50 dBm Adjacent Channel Lower 72 90 dB Upper 72 69 dB Alternate Channel Lower 72 51 dB Upper 72 55 dB POS 20 129 dBm Demo Kit Test Configuration Figure 10 Missing Middle Carrier Test Mode 1 WCDMA Typical Performance With IF 30 72 MHz LO 2 14 GHz 16 TSW3003 Demonstration Kit SLWU029D October 2006 Revised August 2007 Submit Documentation Feedback ...

Страница 17: ...rmance With IF 153 6 MHz LO 2 14 GHz The ACPR has some dependency on the output power of the TSW3003 The RF output spectrum shows some IMD effects as the output power of the DAC is increased The optimum ACPR performance occurs when there is approximately a 6dB attenuation pad between the DAC output and the TRF3703 input As the power is increased the IMD3 effects start to affect the ACPR As the pow...

Страница 18: ...PR vs Pout Baseband 2 14 GHz 30 25 20 15 10 5 Pout dBm Channel dB 11 ACPR 11 Alt ACPR 80 75 65 55 70 60 Demo Kit Test Configuration Figure 12 ACPR Versus Output Power for 1Carrier WCDMA Figure 13 ACPR Versus Output Power for 2 Carriers WCDMA 18 TSW3003 Demonstration Kit SLWU029D October 2006 Revised August 2007 Submit Documentation Feedback ...

Страница 19: ...PR vs Pout Baseband 2 14 GHz 30 25 20 15 10 5 Pout dBm Channel dB 1111 ACPR 1111 Alt ACPR 75 73 71 69 67 65 63 61 59 57 55 Demo Kit Test Configuration Figure 14 ACPR Versus Output Power for 3 Carriers WCDMA Figure 15 ACPR Versus Output Power for 4 Carriers WCDMA SLWU029D October 2006 Revised August 2007 TSW3003 Demonstration Kit 19 Submit Documentation Feedback ...

Страница 20: ...djacent Channel Bandwidth 3 84 MHz Lower 75 95 dB Spacing 5 MHz Upper 75 70 dB Alternate Channel Bandwidth 3 84 MHz Lower 78 95 dB Spacing 10 MHz Upper 79 24 dB Demo Kit Test Configuration Typical ACPR results are shown in Figure 16 through Figure 19 for the four cases Figure 16 Optimum ACPR for 1 Carrier WCDMA 7 dB Pad 20 TSW3003 Demonstration Kit SLWU029D October 2006 Revised August 2007 Submit ...

Страница 21: ...Standard W CDMA 3GPP FWD Tx Channels Ch1 17 55 dBm Ref Ch2 17 58 dBm Total 14 56 dBm Adjacent Channel Lower 71 99 dB Upper 72 00 dB Alternate Channel Lower 74 53 dB Upper 73 88 dB Demo Kit Test Configuration Figure 17 Optimum ACPR for 2 Carrier WCDMA 7 dB Pad SLWU029D October 2006 Revised August 2007 TSW3003 Demonstration Kit 21 Submit Documentation Feedback ...

Страница 22: ...d W CDMA 3GPP FWD Tx Channels Ch1 19 42 dBm Ref Ch2 19 49 dBm Ch3 19 50 dBm Total 14 70 dBm Adjacent Channel Lower 69 45 dB Upper 69 36 dB Alternate Channel Lower 71 60 dB Upper 71 69 dB Demo Kit Test Configuration Figure 18 Optimum ACPR for 3 Carrier WCDMA 7 dB Pad 22 TSW3003 Demonstration Kit SLWU029D October 2006 Revised August 2007 Submit Documentation Feedback ...

Страница 23: ...or 4 Carrier WCDMA 7 dB Pad This section outlines the basic test procedure to get the Demo Kit operational Disconnect the cables at J29 and J30 that connect to the pattern generator Connect the power supply cable and the RF output to the spectrum analyzer Inspect the board to determine which devices were used Note the VCXO frequency U1 that is on the board Engage 6 V power supply Verify the curren...

Страница 24: ...output of the DAC5687 Table 6 Frequency Designations VCO BAND UMTS GSM900 PCS DCS1800 Midband MHz 2140 950 1960 1850 Low MHz 2110 935 1930 1805 High MHz 2170 960 1990 1880 The DAC PLL mode is disabled as per the default jumper settings on J31 See section 6 Verify DACA and DACB Coarse Gain is set to 15 Ensure DAC Offsets and DAC fine gain for both A and B are set to 0 Set the spectrum analyzer as f...

Страница 25: ... Figure 20 Default DAC GUI With fDAC 8 Tone From NCO Figure 21 Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments SLWU029D October 2006 Revised August 2007 TSW3003 Demonstration Kit 25 Submit Documentation Feedback ...

Страница 26: ...ideband The amplitude variation between the two paths can be compensated for by adjusting the DAC fine gain controls or by adjusting the QMC gain controls if the device is operating with the QMC on The phase can be compensated by using the QMC phase adjustment Note this is only possible when the coarse mixer is not used in the fDAC 4 mode Coarse mixing in the fDAC 4 mode causes the relative phase ...

Страница 27: ...significantly Other spurs can be easily filtered out using an RF filter Figure 23 Sideband and LO Compensated Using QMC Settings To configure the board for external LO implement the following modifications SLWU029D October 2006 Revised August 2007 TSW3003 Demonstration Kit 27 Submit Documentation Feedback ...

Страница 28: ...nnect the external LO to modulator external LO J39 Disable the TRF3761 output by setting J31 23 24 PD_OUTBUF J31 25 26 CHIP_EN Figure 24 Board Modifications for External LO Figure 25 Jumper Settings to Disable TRF3761 TSW3003 Demonstration Kit 28 SLWU029D October 2006 Revised August 2007 Submit Documentation Feedback ...

Страница 29: ...3003 Demo Kit layout provides the opportunity to place components to realize up to a 5th order LC filter The Demo Kit is by default populated with a resistive network to provide some attenuation and a two inductor network to compensate for the droop caused by the parasitic board capacitance This provides about 0 5 dB of ripple up to 200 MHz of bandwidth followed by a slow low pass rolloff SLWU029D...

Страница 30: ...T494A106M016AS C83 C84 C101 C116 C122 C148 C150 6 C95 C104 C117 C127 0 001μF 0402 Panasonic ECJ 0EB1E102K C163 C164 1 C102 560pF 0402 Panasonic ECJ 0EB1H561K 1 C108 0 47μF 0603 Murata GRM188R71C474KA88D 1 C110 22μF tant_a Kemet T494A226M010AS 2 C119 C343 100pF 0402 Panasonic ECJ 0EB1E101K 1 C126 680pF 0603 Murata GRM1885C2A681JA01D 1 C128 330pF 0603 Murata GRM1885C2A331JA01D 1 C136 0 033μF 0402 AV...

Страница 31: ...EKF1582V 1 R28 30 1K 0603 Panasonic ERJ 6ENF3012V 1 R29 10 0402 Panasonic ERJ 2RKF10R0X 11 R32 R33 R82 R86 R88 100 0402 Panasonic ERJ 2RKF1000X R89 R92 R93 R96 R99 R125 3 R34 R36 750 0402 Panasonic ERJ 2RKF7500X 8 R39 R44 R47 R49 130 0402 Panasonic ERJ 2RKF1300X 3 R48 R52 R83 150 0402 Panasonic ERJ 2RKF1500X 3 R50 R63 R69 0 0402 Panasonic ERJ 2GE0R00X 8 R53 R56 R58 R59 R70 82 5 0402 Panasonic ERJ ...

Страница 32: ...0 Texas DAC5687 DAC5687 Instruments 1 U12 CDCM7005 QFN48 Texas CDCM7005RGZT Instruments 1 U16 OSC VECTRON OSC_4_SM_460x386 VECTRON VTD3 J0BC 10M000 1 U17 TRF3761 PQFP_40_242x242_0p5mm Texas TRF3761 Instruments 1 U18 TRF3703 33 QFN24 Texas TRF3703 Instruments 1 U47 SN74AHC541PW tssop_20_260x177_26 Texas SN74AHC541PW Instruments 1 U48 SN74HC241PW tssop_20_260x177_26 Texas SN74HC241PW Instruments 3 U...

Страница 33: ...LL_LOCK MS A D E N J27 PLL_LOCK 1 5 2 3 4 C56 1uF C56 1uF C58 1uF C58 1uF C59 1uF C59 1uF U10 DAC5687 U10 DAC5687 DA2 53 DA3 52 DA4 51 DGND 45 DA5 50 DA6 49 DA7 48 AVDD 3 IOGND 47 DB1 72 DB0 LSB 71 DGND 38 DGND 81 IODVDD 80 AGND 17 AVDD 18 AVDD 23 AVDD 24 DA10 41 AGND 25 DVDD 26 IOUTB2 6 DGND 27 SDENB 28 SCLK 29 PLLLOCK 70 DA14 35 RESETB 95 SLEEP 96 DGND 88 IOVDD 46 IOUTB1 5 AGND 9 AVDD 8 PLLVDD 6...

Страница 34: ... of INTERFACE CONTROL D TSW3003_EVM B 2 7 Wednesday March 07 2007 J31 JUMPER PINS 1 2 JUMPER PINS 7 8 JUMPER PINS 11 12 JUMPER PINS 22 23 JUMPER PINS 26 27 JUMPER PINS 31 32 JUMPER PINS 20 21 JUMPER PINS 4 5 R108 22 1 R108 22 1 RN4 4816P 001 220 RN4 4816P 001 220 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RN3 4816P 001 220 RN3 4816P 001 220 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RN2 4816P 001 220 RN2 ...

Страница 35: ...60 4 R184 60 4 R133 634 R133 634 68 ohm 100MHz FB5 68 ohm 100MHz FB5 C340 4 7pF DNI C340 4 7pF DNI R118 634 R118 634 R134 634 R134 634 R179 0 R179 0 L26 33nH L26 33nH 1 2 R236 0 R236 0 C225 4 7pF DNI C225 4 7pF DNI R119 634 R119 634 R180 60 4 R180 60 4 R172 115 R172 115 C162 1uF C162 1uF C343 100pF C343 100pF L22 0 L22 0 1 2 R177 115 R177 115 68 ohm 100MHz FB4 68 ohm 100MHz FB4 C163 1000pF C163 10...

Страница 36: ...uF 10V C101 10uF 10V R40 130 R40 130 JP2 VCXO JP2 VCXO 1 3 2 U1 2111 491 52MHZ U1 2111 491 52MHZ V_CTRL 1 NC 2 GND 3 OUT 4 OUTB 5 VCC 6 R56 82 5 R56 82 5 R53 82 5 R53 82 5 C94 1uF C94 1uF C97 1uF C97 1uF MS A D E N J8 OUTCLK3 MS A D E N J8 OUTCLK3 1 5 2 3 4 C93 1uF C93 1uF D14 LED green LOCK D14 LED green LOCK C98 1uF C98 1uF C99 1uF C99 1uF D12 LED green VCXO D12 LED green VCXO R55 82 5 R55 82 5 ...

Страница 37: ...0 R125 100 R84 10K R84 10K R68 22 1 R68 22 1 R92 100 R92 100 R67 22 1 R67 22 1 R81 10K R81 10K R75 22 1 R75 22 1 C344 1uF C344 1uF R82 100 R82 100 R72 22 1 R72 22 1 U50 FT245RL U50 FT245RL USBDM 16 USBDP 15 VCCIO 4 NC1 8 RESET 19 NC2 24 OSCI 27 OSCO 28 3V3OUT 17 AGND 25 GND 7 GND 18 GND 21 TEST 26 PWREN 12 WR 14 D1 5 D7 6 D5 9 D6 10 TXE 22 D4 2 D3 11 RXF 23 D0 1 RD 13 VCC 20 D2 3 68 OHM 100MHz FB6...

Страница 38: ...10uF 10 16V 1 2 C43 1uF 10 16V C43 1uF 10 16V 1 2 C19 10uF 10 16V C19 10uF 10 16V 1 2 C36 1uF 10 16V C36 1uF 10 16V 1 2 R21 100K R21 100K C5 01uF C5 01uF R109 300 R109 300 C35 10uF 10 16V C35 10uF 10 16V 1 2 C18 47uF 10V 20 C18 47uF 10V 20 R18 100K R18 100K C348 10uF 10 16V C348 10uF 10 16V 1 2 R27 15 8K R27 15 8K C28 1uF 10 16V C28 1uF 10 16V 1 2 U9 TPS76750QPWP U9 TPS76750QPWP GND HTSNK2 2 NC3 1...

Страница 39: ... C126 680pF C126 680pF C121 1uF C121 1uF C154 10pF C154 10pF L27 8 2nH L27 8 2nH 1 2 C123 1uF C123 1uF R95 10K R95 10K R107 4 75K R107 4 75K U16 OSC VECTRON U16 OSC VECTRON REF 1 GND 4 VDD 8 OUT 5 L28 8 2nH L28 8 2nH 1 2 C120 1uF C120 1uF SCREW PANHEAD 4 40 x 3 8 SCREW PANHEAD 4 40 x 3 8 C119 100pF C119 100pF R110 649 R110 649 U53 OSC VECTRON DNI U53 OSC VECTRON DNI REF 1 GND 2 VDD 4 OUT 3 R288 6 ...

Страница 40: ...to handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which...

Страница 41: ...ice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyer...

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