9
SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Specifications
Copyright © 2011–2020, Texas Instruments Incorporated
(1)
Antenna driver output resistance
(2)
Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1
(3)
Depending on the crystal parameters and components
(4)
Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400
Ω
(12-ns time constant when 30-pF load is used).
5.4
Electrical Characteristics
TYP operating conditions are T
A
= 25°C, V
IN
= 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
PD1
Supply current in power down mode 1
All building blocks disabled, including supply-
voltage regulators; measured after 500-ms
settling time (EN = 0, EN2 = 0)
<0.5
5
µA
I
PD2
Supply current in power down mode 2
(sleep mode)
The SYS_CLK generator and VDD_X remain
active to support external circuitry, measured
after 100-ms settling time (EN = 0, EN2 = 1)
120
200
µA
I
STBY
Supply current in standby mode
Oscillator running, supply-voltage regulators in
low-consumption mode (EN = 1, EN2 = x)
1.9
3.5
mA
I
ON1
Supply current without antenna driver
current
Oscillator, regulators, RX, and AGC are active,
TX is off
10.5
14
mA
I
ON2
Supply current in TX (half power)
Oscillator, regulators, RX, AGC, and TX
active, P
OUT
= 100 mW
70
78
mA
I
ON3
Supply current in TX (full power)
Oscillator, regulators, RX, AGC, and TX
active, P
OUT
= 200 mW
130
170
mA
V
POR
Power-on reset voltage
Input voltage at VIN
1.4
2
2.6
V
V
BG
Bandgap voltage (pin 11)
Internal analog reference voltage
1.5
1.6
1.7
V
V
DD_A
Regulated output voltage for analog
circuitry (pin 1)
V
IN
= 5 V
3.1
3.5
3.8
V
V
DD_X
Regulated supply for external circuitry
Output voltage pin 32, V
IN
= 5 V
3.1
3.4
3.8
V
I
VDD_Xmax
Maximum output current of VDD_X
Output current pin 32, V
IN
= 5 V
20
mA
R
RFOUT
Antenna driver output resistance
(1)
Half-power mode, V
IN
= 2.7 V to 5.5 V
8
12
Ω
Full-power mode, V
IN
= 2.7 V to 5.5 V
4
6
R
RFIN
RX_IN1 and RX_IN2 input resistance
4
10
20
k
Ω
V
RF_INmax
Maximum RF input voltage at RX_IN1
or RX_IN2
V
RF_INmax
should not exceed VIN
3.5
V
pp
V
RF_INmin
Minimum RF input voltage at RX_IN1
or RX_IN2 (input sensitivity)
(2)
f
SUBCARRIER
= 424 kHz
1.4
2.5
mV
pp
f
SUBCARRIER
= 848 kHz
2.1
3
f
SYS_CLK
SYS_CLK frequency
In power mode 2, EN = 0, EN2 = 1
25
60
120
kHz
f
C
Carrier frequency
Defined by external crystal
13.56
MHz
t
CRYSTAL
Crystal run-in time
Time until oscillator stable bit is set (register
0x0F)
(3)
5
ms
f
D_CLKmax
Maximum DATA_CLK frequency
(4)
Depends on capacitive load on the I/O lines,
recommendation is 2 MHz
(4)
2
4
10
MHz
V
IL
Input voltage, logic low
I/O lines, IRQ, SYS_CLK, DATA_CLK, EN,
EN2
0.2 ×
V
DD_I/O
V
V
IH
Input voltage threshold, logic high
I/O lines, IRQ, SYS_CLK, DATA_CLK, EN,
EN2
0.8 ×
V
DD_I/O
V
R
OUT
Output resistance, I/O_0 to I/O_7
500
800
Ω
R
SYS_CLK
Output resistance R
SYS_CLK
200
400
Ω
