Texas Instruments TRF3765 Series, Руководство пользователя, Страница: 15 / 21

www.ti.com
Troubleshooting FAQs
5 Troubleshooting FAQs
This section provides troubleshooting sequences in Table 5 to resolve several of the most frequently
asked questions.
Table 5. Troubleshooting Sequences
Problem Response
Verify that the loop filter components correspond to the programmed PFD frequency.
Check power on device pin test points: TP12. TP13.TP19-TP23
Verify that one refclk is applied, generated either onboard or offboard.
Registers 1 to 6 must be initialized. Reload the start-up macro. Execute VCO calibration after
initialization is complete.
Fractional mode operation must set LD_ANA_PREC* at low precision (1).
LD diode D2 won't light up
Verify GUI communication with the device. Readback value fields display nonzero hexadecimal
values after a register is written. The GUI Low Level display allows direct register readback.
Using the GUI Low Level tab, read registers. Verify that read ADDR bits are correct and that no N.U.
bits have been initialized. Reset the device by removing power if a faulty address has been sent to
the device or if any N.U. bits have been set.
Measure voltage on TP8. Multimeter measurements below 2 V but above 0.5 V indicate toggling LD.
Verify Cal_Clk frequency.
High Level tab readback is supported on GUI revision 6 or later. Low Level readback is supported on
all GUI releases.
No readback from registers Prerelease device revisions may not support readback. Verify the device markings do not include a
P prefix on the first line.
On the GUI Start Up tab, Disconnect, verify that Simulate Connection is not selected, then Connect.
Verify that the buffer is configured to be powered on by reading back register 4 on the GUI Low
Level tab. 0 = on, and 1 = off.
No LO output
Verify that registers are successfully reading back from the device to confirm communication.
Check power on device pin test points: TP12, TP13, TP19-TP23
Verify that one refclk is applied, generated either onboard or offboard.
Remove any monitoring equipment from the VTune tap on TP12.
Spurs or unstable output
Verify that EN_DITH, EN_ISOURCE are set properly for integer or fractional mode. Verify
frequency
VCO_BIAS is set properly for the applied VCC_TK voltage level. In fractional mode, verify that
MOD_ORD is third (2) and DITH_SEL is Random (0).
Eliminate ground loops in power supplies.
Verify that the installed loop filter corresponds to the applied refclk and PFD frequency.
Verify that the power supply is clean and is not an unfiltered switching power supply.
Poor phase noise
Revert the board to shipping hardware configuration, load a factory-supplied, start-up file, and verify
phase noise against data sheet measurements.
15 SLWU076A – November 2011 – Revised July 2012 TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated