background image

3 Schematic

1

2

3

4

5

6

7

8

9

10

J2

P MBus

PMBus

PGND

Gre e n

2

1

LED1

1.00k

R42

47uF

C33

47uF

C29

47uF

C34

47uF

C35

47uF

C31

47uF

C30

47uF

C32

47uF

C26

47uF

C36

47uF

C20

47uF

C27

47uF

C28

PGND

VOUT_A

47uF

C55

47uF

C51

47uF

C56

47uF

C57

47uF

C53

47uF

C52

47uF

C54

47uF

C48

47uF

C58

47uF

C59

47uF

C49

47uF

C50

PGND

VOUT_B

VOUT_A

VOS NS_A

TP 1

PVIN

TP 8

CHB_VoutA

TP 2

PGND

100uF

C8

100uF

C7

PGND

TP 7

CHA_VoutA

1
2

T4

AVIN

PGND

PGND

Bode_Input

TP24

CLK

TP23

CNTL

TP26
DATA

TP25
S MBALRT

1

2

S MB1

VOUT_A

TP16

PGND

TP4

PGND

PGND

1
2

T1

PVIN

1
2

T2

PGND

47uF

C15

47uF

C16

47uF

C17

47uF

C18

47uF

C19

47uF

C37

47uF

C63

47uF

C64

47uF

C65

47uF

C66

47uF

C67

47uF

C68

47uF

C21

47uF

C22

47uF

C69

47uF

C70

PGND

VOUT_A

TP 5

Re mote S e ns e Vout A (+)

TP 9

Re mote S e ns e Vout A (-)

VOUT_B

S MBALT

CLK

DATA

CNTL

PGND

1

2

J P8

P MBus  to AVIN

VBUS

1

D-

2

D+

3

ID

4

GND

5

6

7

8

11

10

9

J1

Micro-USB P owe r

PGND

1

2

J P7

USB to P VIN

PVIN

PVIN

30V

D1

30V

D2

HW1
BS R192A_Ha rdwa re .SchDoc

Input: 2.95 V to 16 V

Output: 0.6 V to 3.6 V at 35 A

PGND

SYNC

29

EN_B

25

SMB_ALRT_A

6

P GND

1

AGND_A

21

P GND

4

AGND_B

27

P VIN_A

18

AVIN_A

20

PMB_DATA_A

8

P VIN_A

55

P VIN_B

24

P VIN_B

56

PMB_CLK_A

7

VOSNS_A

2

VOUT_A

50

VOUT_A

51

P GND

52

BCX_CLK_A

11

S W_A

53

P GND

17

P GND

23

P GND

43

S W_B

58

VOUT_B

47

VOUT_B

48

P GND

49

AVIN_B

26

VOSNS_B

45

P GND

46

P GD/RS T_A

9

P GND

30

EN_A

19

PMB_DATA_B

39

PMB_CLK_B

40

SMB_ALRT_B

41

BCX_DATA_A

10

BCX_CLK_B

36

P GD/RS T_B

38

BCX_DATA_B

37

P GND

54

P GND

57

P GND

59

VDD5_A

22

BP1V5_A

5

VSEL_A

15

ADRSEL_A

14

MSEL1_A

13

VSHARE_A

12

MSEL2_A

16

VDD5_B

28

GOSNS /FLWR_A

3

BP1V5_B

42

GOSNS /FLWR_B

44

VSHARE_B

35

MSEL2_B

31

VSEL_B

32

ADRSEL_B

33

MSEL1_B

34

U1

TP S M8D6x24MOW59

AVIN_B

ADRSEL_A

MSEL2_A
VSEL_A

53.6k

R18

MSEL1_A

14.7k

R22

14.7k

R24

0

R21

22uF

C5

22uF

C4

6800pF

C6

22uF

C2

100uF

C1

22uF

C3

PVIN

PGND

PGND

P VIN_A

P VIN_A

PGND

AGND_A

AVIN_A

PGND

22uF

C13

22uF

C12

6800pF

C14

22uF

C10

100uF

C9

22uF

C11

PVIN

PGND

PGND

P VIN_B

PGND

PGND

AGND_B

AVIN_B

P VIN_B

CLK

DATA

DATA

CLK

S MBALT

S MBALT

PGND

0.1uF

C41

P VIN_A

30.1k

R2

PGND

1

2

3

4

5

6

J P3

EN_A

EN_A

VOS NS_A
S W_A

VOUT_A

GOS NS_A

10

R3

10

R1

1
2
3

J P2

AVIN_B

1
2
3

J P1

AVIN_A

AVIN_A

0

R26

VS HARE_A

VS HARE_A

ADRSEL_B

MSEL2_B
VSEL_B

53.6k

R30

MSEL1_B

14.7k

R35

0

R32

Output: 0.6 V to 3.6 V at 35 A

TP 6

VOUT_A

TP 10

PGND

S W_B

VOS NS_B

VOUT_B

GOS NS_B

BP1V5_A

VDD5_A

EN_B

PGND

0.1uF

C43

P VIN_B

30.1k

R6

1

2

3

4

5

6

J P4

EN_B

PGND

BP1V5_B

VDD5_B

VSEL_A = 0.8V Output

VSEL_B = 1.2V Output

0

R19

TP 15
SYNC

SYNC

0

R20

BCX_CLK_A

BCX_CLK_B

BCX_DATA_A

BCX_DATA_B

P GD_A

P GD_B

0.022uF

C44

0.022uF

C45

VS HARE_B

BCX_CLK_B

BCX_DATA_B

10.0k

R31

10.0k

R25

VDD5_A

VDD5_B

1
2

J P5

VDD5_A

BP1V5_A

BP1V5_B

AGND_A

AGND_B

TP 12

VS HARE_A

TP 13

VS HARE_B

PGND

VDD5_A

1
2

J P6

VDD5_B

PGND

VDD5_B

TP11

PGood_A

TP14

PGood_B

AVIN

VOUT_B

VOS NS_B

TP20

CHB_VoutB

TP19

CHA_VoutB

PGND

Bode_Input

1

2

S MB2

VOUT_B

TP 17

Re mote S e ns e Vout B (+)

TP 21

Re mote S e ns e Vout B (-)

TP 18

VOUT_B

TP 22

PGND

0.022uF

C71

0.022uF

C72

1

2

T5

VOUT_A

1

2

T6

PGND

TP 27

PGND

PGND

100pF

C42

100pF

C23

1

2

T7

VOUT_B

1

2

T8

PGND

470uF

C39

470uF

C40

470uF

C61

470uF

C62

10

µ

F

C25

10

µ

F

C24

10

µ

F

C47

10

µ

F

C46

47uF

C38

47uF

C60

PVIN

11.0k

R4

11.0k

R8

1
2

T3

PGND

AVIN

GOS NS_A

GOS NS_B

BP1V5_A

BP1V5_B

NT1

Ne t-Tie

NT2

Ne t-Tie

NT4

Ne t-Tie

NT3

Ne t-Tie

49.9

R9

49.9

R12

49.9

R10

49.9

R13

10.0

R7

10.0

R14

49.9

R37

49.9

R39

49.9

R38

49.9

R40

10.0

R36

10.0

R41

10.0k

R5

10.0k

R11

CNTL

CNTL

68.1k

R33

10.0k

R27

10.0k

R28

10.0k

R17

10.0k

R16

10.0k

R15

10.0k

R23

26.1k

R29

26.1k

R34

SW_A and SW_B have a via test point on the bottom of the PCB

TP3

PGND

Figure 3-1. TPSM8D6C24EVM-2V0 Schematic

www.ti.com

Schematic

SLUUCK6 – DECEMBER 2021

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TPSM8D6C24EVM-2V0 User's Guide

5

Copyright © 2021 Texas Instruments Incorporated

Содержание TPSM8D6C24EVM-2V0

Страница 1: ...ent Procedure 9 6 2 Efficiency Measurement Test Points 9 6 3 Control Loop Gain and Phase Measurement Procedure 10 7 Performance Data and Typical Characteristic Curves 11 7 1 Efficiency 11 7 2 Load Reg...

Страница 2: ...M8D6C24EVM 2V0 Internal Layer 4 Top View 17 Figure 8 8 TPSM8D6C24EVM 2V0 Internal Layer 5 Top View 17 Figure 8 9 TPSM8D6C24EVM 2V0 Internal Layer 6 Top View 18 Figure 8 10 TPSM8D6C24EVM 2V0 Internal B...

Страница 3: ...aces or sharp edges Do not reach under the board during operation CAUTION The circuit module may be damaged by over temperature To avoid damage monitor the temperature during evaluation and provide co...

Страница 4: ...3 and JP4 in UVLO position 3 50 V Output Characteristics VOUT_A output voltage VOUTA 0 8 V VOUT_B output voltage VOUTB 1 2 V VOUT_A output load current IOUTA 0 35 A VOUT_B output load current IOUTB 0...

Страница 5: ...F C6 22uF C2 100uF C1 22uF C3 PVIN PGND PGND PVIN_A PVIN_A PGND AGND_A AVIN_A PGND 22uF C13 22uF C12 6800pF C14 22uF C10 100uF C9 22uF C11 PVIN PGND PGND PVIN_B PGND PGND AGND_B AVIN_B PVIN_B CLK DATA...

Страница 6: ...ge Source The input voltage source VIN must be a 0 V to 18 V variable DC source capable of supplying a minimum of 8 ADC to support 35 A load with 5 V input or 16 ADC to support a combined 70 A load Co...

Страница 7: ...point Sensitive signal TP13 VSHARE_B VSHARE_B measurement point Sensitive signal TP14 PGood_B PGOOD signal of VOUT_B TP15 SYNC External clock input SYNC IN or output to synchronize other devices SYNC...

Страница 8: ...5 VOUT_A VOUT connector T6 T8 PGND VOUT connector 4 4 Evaluating Split Rail Input The default configuration of the EVM is for single rail input Split rail input enables operation with 3 3 V PVIN For s...

Страница 9: ...and inductor it is important to measure the voltages at the correct location This is necessary because otherwise the measurements will include losses that are not related to the power train itself Lo...

Страница 10: ...esulting output of VOUT_A Bode can be measured by a network analyzer with a CH_B CH_A configuratio n VOUT_B TP19 CHA_VoutB Input to feedback divider of VOUT_B The amplitude of the perturbation at this...

Страница 11: ...803 0 8035 0 804 0 8045 0 805 PVIN 5 V PVIN 12 V PVIN 16 V Figure 7 3 VOUT_A Load Regulation Output Current A Output Voltage V 0 5 10 15 20 25 30 35 1 2 1 2005 1 201 1 2015 1 202 1 2025 1 203 1 2035...

Страница 12: ...nsient Response Figure 7 8 VOUT_B Transient Response 7 5 Control Loop Bode Plot Figure 7 9 VOUT_A Bode Plot 35 A Load Figure 7 10 VOUT_B Bode Plot 35 A Load Performance Data and Typical Characteristic...

Страница 13: ...pple No Load Figure 7 12 VOUT_B Output Ripple No Load Figure 7 13 VOUT_A Output Ripple 35 A Load Figure 7 14 VOUT_B Output Ripple 35 A Load www ti com Performance Data and Typical Characteristic Curve...

Страница 14: ...5 A CC Load 7 8 Control Off Figure 7 17 and Figure 7 18 illustrate the control off waveforms at 35 A outputs Figure 7 17 VOUT_A Shutdown From Control 35 A CC Load Figure 7 18 VOUT_B Shutdown From Cont...

Страница 15: ...N 12 V IOUTA 35 A IOUTB 35A Airflow 200 LFM 10 minute soak Figure 7 19 Thermal Image www ti com Performance Data and Typical Characteristic Curves SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D...

Страница 16: ...Component View Top View Figure 8 2 TPSM8D6C24EVM 2V0 Bottom Side Component View Bottom View Figure 8 3 TPSM8D6C24EVM 2V0 Top Copper Top View Figure 8 4 TPSM8D6C24EVM 2V0 Internal Layer 1 Top View EVM...

Страница 17: ...r 3 Top View Figure 8 7 TPSM8D6C24EVM 2V0 Internal Layer 4 Top View Figure 8 8 TPSM8D6C24EVM 2V0 Internal Layer 5 Top View www ti com EVM Assembly Drawing and PCB Layout SLUUCK6 DECEMBER 2021 Submit D...

Страница 18: ...Top View Figure 8 10 TPSM8D6C24EVM 2V0 Internal Bottom Layer Top View EVM Assembly Drawing and PCB Layout www ti com 18 TPSM8D6C24EVM 2V0 User s Guide SLUUCK6 DECEMBER 2021 Submit Document Feedback C...

Страница 19: ...AP CERM 47 F 10 V 10 X7R 1210 1210 GRM32ER71A476KE15L MuRata C23 C42 2 100 pF CAP CERM 100 pF 50 V 10 X7R 0402 402 8 85012E 11 Wurth Elektronik C24 C25 C46 C47 4 10 F CAP CERM 10 F 10 V 20 X7R 0603 60...

Страница 20: ...1 W AEC Q200 Grade 0 0603 603 CRCW060310R0JNEA Vishay Dale R2 R6 2 30 1 k RES 30 1 k 1 0 1 W 0603 603 RC0603FR 0730K1L Yageo R4 R8 2 11 0 k RES 11 0 k 1 0 1 W 0603 603 RC0603FR 0711KL Yageo R7 R14 R36...

Страница 21: ...Testpoint 5010 Keystone TP2 TP3 TP4 TP10 TP16 TP22 TP27 7 Test Point Multipurpose Black TH Black Multipurpose Testpoint 5011 Keystone TP5 TP7 TP8 TP9 TP11 TP12 TP13 TP14 TP15 TP17 TP19 TP20 TP21 TP23...

Страница 22: ...R28 0 10 0 k RES 10 0 k 1 0 1 W 0603 603 RCG060310K0FKEA Vishay Draloric R18 R30 0 53 6 k RES 53 6 k 1 0 1 W AEC Q200 Grade 0 0603 603 CRCW060353K6FKEA Vishay Dale R26 0 0 RES 0 5 0 1 W AEC Q200 Grad...

Страница 23: ...to find TPSM8D6C24 The EVM needs power to be recognized by the Fusion GUI See Section 5 for the recommended procedure Figure 10 1 Select Device Scanning Mode www ti com Using the Fusion GUI SLUUCK6 DE...

Страница 24: ...r device and the loop follower device are tied to same bus interface In a two phase stacking system the loop controller device will receive and respond to all PMBus communication and loop follower dev...

Страница 25: ...Figure 10 3 Configure ON_OFF_CONFIG www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 User s Guide 25 Copyright 2021 Texas Instruments Incorporated...

Страница 26: ...Compensation Vout Mode and Vout Scale Loop To change these settings to a new value click on Stop Power Conversion then Close and continue The GUI will automatically disable conversion write the new va...

Страница 27: ...ed are found and configured on the SMBALERT Mask tab Figure 10 5 Figure 10 5 Configure SMBALERT Mask www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 Us...

Страница 28: ...cale Loop Vout Transition Rate and Iout Cal Offset are found on the Device Info tab see Figure 10 6 Figure 10 6 Configure Device Info Using the Fusion GUI www ti com 28 TPSM8D6C24EVM 2V0 User s Guide...

Страница 29: ...b see Figure 10 7 to calibrate the IOUT Temp of each phase Figure 10 7 Phase Commands www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 User s Guide 29 C...

Страница 30: ...the configurable parameters which also shows other details like Hex encoding Figure 10 8 Configure All Config Using the Fusion GUI www ti com 30 TPSM8D6C24EVM 2V0 User s Guide SLUUCK6 DECEMBER 2021 S...

Страница 31: ...m some of the PMBus commands at power up The EEPROM Value column shows the values currently configured to the related PMBus commands Figure 10 9 Configure Pin Strapping www ti com Using the Fusion GUI...

Страница 32: ...data Quick access to On Off Config Control pin activation and OPERATION command Margin control Clear Fault Selecting Clear Faults clears any prior fault flags With two devices stacked together the Io...

Страница 33: ...er left corner Figure 10 11 shows the status of the device Figure 10 11 Status Screen www ti com Using the Fusion GUI SLUUCK6 DECEMBER 2021 Submit Document Feedback TPSM8D6C24EVM 2V0 User s Guide 33 C...

Страница 34: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Страница 35: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Страница 36: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Страница 37: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Страница 38: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Страница 39: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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