background image

PXIe-5162_CH0

PXIe-5162_CH1

PXIe-5162_CH2

PXIe-5162_CH3

OUTA

OUTB

SRA

SRB

0

R48

VLDO

REFCAP

VIN

EN

HICC

FAULT

SP

RT

PS

SYNC

LEB

RSC

VLDO

COMP_BUFFER

VSENSE

SS_BUFFER

0

R60

0

R75

0

R54

0

R68

0

R78

0

R81

0

R84

0

R49

0

R55

0

R61

0

R69

0

R76

0

R79

0

R82

0

R85

0

R74

0

R77

0

R80

0

R83

PXIe-5110_CH0

PXIe-5110_CH1

0

R53

OUTA

SRA

0

R52

DNP

0

R59

OUTB

SRB

0

R58

DNP

DMM_Site1_1

DMM_Site1_2

DMM_Site1_3

AWG_CH1_to_SIte1

PXIe-5172-1_CH1_Site1

PXIe-5172-1_CH3_Site1

PXIe-5172-1_CH5_Site1

PXIe-5172-1_CH7_Site1

PXIe-5172-2_CH1_Site1

PXIe-5172-2_CH3_Site1

PXIe-5172-2_CH5_Site1

PXIe-5172-2_CH7_Site1

DMM_Site1_4

DMM_Site1_5

AWG_CH2_to_SIte1

PXIe-5172-1_CH0_Site1

PXIe-5172-1_CH2_Site1

PXIe-5172-1_CH4_Site1

PXIe-5172-1_CH6_Site1

PXIe-5172-2_CH0_Site1

PXIe-5172-2_CH2_Site1

PXIe-5172-2_CH4_Site1

PXIe-5172-2_CH6_Site1

1

2

3

4

5

OPA354AIDBVR

U5

100nF
25V

C26

DNP

0

R96

0

R86

0

R94

0

R97

DNP

4

1

2

SN74AHCT1G08DCKR

U2A

VCC

5

GND

3

SN74AHCT1G08DCKR

U3B

4

1

2

SN74AHCT1G08DCKR

U3A

VCC

5

GND

3

SN74AHCT1G08DCKR

U2B

AGND

AGND

AGND

AGND

OUTA

SRA

OUTB

SRB

PXIe-5162_CH0

PXIe-5162_CH1

0

R63

0

R70

PXIe-5162_CH0

PXIe-5162_CH1

4

1

2

SN74AHCT1G08DCKR

U2A

U

U

VCC

5

GND

3

SN74AHCT1G08DCKR

U3B

4

1

2

SN74AHCT1G08DCKR

U3A

VCC

5

GND

3

SN74AHCT1G08DCKR

U2B

U

U

AGND

AGND

AGND

AGND

OUTA

T

T

SRA

R

R

OUTB

SRB

0

R63

0

R70

PXIe-5162_CH0

PXIe-5162_CH1

Cross Conduction Trigger

In Case Cross Conduction in A, we send trigger to C

H1 and we capture OUTA-CH0 and SRA-CH2

In Case Cross Conduction in B, we send trigger to C

H0 and we capture OUTB-CH1 and SRB-CH3

COMP

COMP_BUFFER

AGND

AGND

1

2

3

4

5

OPA35

A

A

4AIDBVR

U5

100nF
25V

C26

D

D

D

D

DN

N

N

N

NP

P

P

P

P

0

R96

0

R86

0

R94

0

R97

D

D

D

D

D

DN

N

N

N

N

NP

P

P

P

P

COMP

COMP_BUFFER

AGND

AGND

C

O

M

P

B

u

ff

e

r

Do we Need a HS Comparator to Adjust VIH??

PXIe-5110_CH0

PXIe-5110_CH1

0

R53

OUTA

T

T

SRA

R

R

0

R52

D

D

D

D

D

DN

N

N

NP

P

P

P

0

R59

OUTB

SRB

0

R58

D

D

D

D

D

DN

N

N

NP

P

P

P

PXIe-5110 (PWM Trigger Supported)

PXIe-5162_CH0

PXIe-5162_CH1

PXIe-5162_CH2

PXIe-5162_CH3

OUTA

T

T

OUTB

SRA

R

R

SRB

0

R74

0

R77

0

R80

0

R83

PXIe-5162_CH0

PXIe-5162_CH1

PXIe-5162 (HS Scope) or DPO7XXXX Series

0

R48

VLDO

REFCAP

VIN

EN

RSC

COMP_BUFFER

VSENSE

SS_BUFFER

0

R60

0

R75

0

R54

0

R68

0

R78

0

R81

0

R84

PXIe-5172-1_CH1_Site1

PXIe-5172-1_CH3_Site1

PXIe-5172-1_CH5_Site1

PXIe-5172-1_CH7_Site1

PXIe-5172-1_CH0_Site1

PXIe-5172-1_CH2_Site1

PXIe-5172-1_CH4_Site1

PXIe-5172-1_CH6_Site1

PXIe-5172 (General Purpose Up to 100MHz)

HICC

FAULT

SP

RT

PS

SYNC

LEB

VLDO

0

R49

0

R55

0

R61

0

R69

0

R76

0

R79

0

R82

0

R85

PXIe-5172-2_CH1_Site1

PXIe-5172-2_CH3_Site1

PXIe-5172-2_CH5_Site1

PXIe-5172-2_CH7_Site1

PXIe-5172-2_CH0_Site1

PXIe-5172-2_CH2_Site1

PXIe-5172-2_CH4_Site1

PXIe-5172-2_CH6_Site1

PXIe-5172 (General Purpose Up to 100MHz)

0

R57

DNP

OUTA

SRA

0

R51

DNP

0

R73

DNP

OUTB

SRB

0

R65

DNP

OUTA

OUTB

SRA

SRB

0

R50

DNP

0

R56

DNP

0

R64

DNP

0

R72

DNP

SYNC

0

R89

CS_ILIM

0

R92

AW

A

A

G_CH1_to_

_

SIte1

AW

A

A

G_CH2_to_

_

SIte1

SYNC

0

R89

CS_ILIM

0

R92

External CLK Syncronization

0

R87

0

R88

0

R90

0

R91

0

R93

VLDO

REFCAP

VIN

COMP_BUFFER

DMM_Site1_1

DMM_Site1_2

DMM_Site1_3

DMM_Site1_4

DMM_Site1_5

0

R87

0

R88

0

R90

0

R91

0

R93

VLDO

REFCAP

VIN

COMP_BUFFER

DMM

PXIe-5922_CH0_Site1

PXIe-5922_CH1_Site1

1

2

3

4

5

OPA354AIDBVR

U6

100nF
25V

C34

DNP

0

R106

0

R104

0

R105

0

R107

DNP

SS

SS_BUFFER

AGND

AGND

1

2

3

4

5

OPA35

A

A

4AIDBVR

U6

100nF
25V

C34

D

D

D

D

D

DN

N

N

N

N

N

N

NP

P

P

P

P

0

R106

0

R104

0

R105

0

R107

D

D

D

D

D

DN

N

N

N

N

NP

P

P

P

P

SS

SS_BUFFER

AGND

AGND

S

S

B

u

ff

e

r

SS_BUFFER

0

R102

0

R99

COMP_B_IN

TP17

COMP_B_OUT

TP16

100nF
25V

C20

1µF
50V

C21

1nF
50V

C22

1µF
50V

C24

1nF
50V

C25

100nF
25V

C23

1µF
50V

C28

1nF
50V

C29

100nF
25V

C27

1µF
50V

C36

1nF
50V

C37

100nF
25V

C35

100nF
25V

C39

DNP

AGND

100nF
25V

C38

DNP

100nF
25V

C32

DNP

100nF
25V

C33

DNP

AGND

SS_B_IN

TP19

SS_B_OUT

TP18

SS_BUFFER

COMP_BUFFER

PXIe-5922_CH0_Site1

PXIe-5922_CH1_Site1

0

R102

0

R99

SS_BUFFER

COMP_BUFFER

PXIe-5922 (High Presicion)

0

R62

0

R66

0

R67

0

R71

1

3
2

GND

10

R100

Heater

AGND

PXIe-4139-1 F+

PXIe-4139-1 S+

0

R103

0

R101

PXIe-4139-1 S-

0

R98

1

3
2

GND

10

R100

Heater

AGND

PXIe-4139-1 F+

PX

P

P Ie-4

X

X

139-1 S+

0

R103

0

R101

PX

P

P Ie-4

X

X

139-1 S-

0

R98

IN

3

OUT

2

1

TAB

4

GND

LM1117MPX-5.0

U4

E36311A-1 (+25V)

AGND

10V
47uF

C31

AGND

+5V

+5V

+5V

+5V

0

R95

E36311A-1 (+25V)

+5V

IN

3

OUT

2

1

TA

T

T B

4

GND

G

G

LM1117MPX-5

X

X .0

U4

U

U

E36311A-1

A

A

(+25V)

AGND

10V
47uF

C31

AGND

+5V

0

R95

E36311A-1

A

A

(+25V)

+5V

LDO

35V
100µF

C30

AGND

RSC

TP21

LEB

TP27

PS

TP26

RT

TP25

SP

TP24

FAULT

TP23

HICC

TP22

VSENSE

TP20

Figure 5-2. TPS7H5001-SP Schematic (Page 2)

Schematics

www.ti.com

10

TPS7H5001-SP Evaluation Module

SLVUBZ8 – JULY 2021

Submit Document Feedback

Copyright © 2021 Texas Instruments Incorporated

Содержание TPS7H5001-SP

Страница 1: ...ure 2 2 TPS7H5001 SP Output 4 Figure 2 3 Duty Cycle Generation 4 Figure 4 1 Top Overlay 7 Figure 4 2 Top Solder 7 Figure 4 3 Top Layer 7 Figure 4 4 Bottom Layer 7 Figure 4 5 Bottom Solder 8 Figure 4 6...

Страница 2: ...the TPS7H5001 SP without additional hardware Minor changes were made to the BOM for manufacturability purposes 1 1 Features This EVM has the following features Synchronous rectification outputs with a...

Страница 3: ...V input at 10 mA See Positive and Negative Terminal for J11 for connections TP9 COMP 1 V at 10 mA Input range can be 0 3 V to 3 3 V based on the TPS7H5001 SP Radiation Hardness Assured Si and GaN Dua...

Страница 4: ...on the input voltage on COMP as well as the triangle waveform created by the CS_LIM circuit or any other waveform that the user decides to add to the CS_LIM pin See Duty Cycle Generation for signal g...

Страница 5: ...7H5001 SP forcing this voltage runs the TPS7H5001 SP in open loop TP10 REFCAP Internal reference for TPS7H5001 SP TP11 TP12 SS In a closed loop design this slowly increases converter output voltage du...

Страница 6: ...n Table 3 2 J6 Connections and Configuration Pin Connection Duty Cycle Limit Configuration Description Pin 1 and Pin 2 100 DCL is connected high to VLDO Pin 2 and Pin 3 50 DCL is connected low to AVSS...

Страница 7: ...e EVM PCB layout images Figure 4 1 Top Overlay Figure 4 2 Top Solder Figure 4 3 Top Layer Figure 4 4 Bottom Layer www ti com PCB Layouts SLVUBZ8 JULY 2021 Submit Document Feedback TPS7H5001 SP Evaluat...

Страница 8: ...Figure 4 6 Bottom Overlay Figure 4 7 Drill Drawing Figure 4 8 Board Dimensions PCB Layouts www ti com 8 TPS7H5001 SP Evaluation Module SLVUBZ8 JULY 2021 Submit Document Feedback Copyright 2021 Texas...

Страница 9: ...GND OUTB 1 2 3 4 5 J3 AGND 1 2 3 4 5 J4 AGND SRA SRB OUTA TP1 EN TP8 SRA TP3 OUTB TP2 SRB TP4 20pF C5 1 00M R5 D DN N N N N NP 1 00M 1 00M R5 R5 AGND OUTA OUTB 20pF C6 1 00M R6 D DN N N N N N NP 1 00M...

Страница 10: ...XIe 5172 1_CH3_Site1 PXIe 5172 1_CH5_Site1 PXIe 5172 1_CH7_Site1 PXIe 5172 1_CH0_Site1 PXIe 5172 1_CH2_Site1 PXIe 5172 1_CH4_Site1 PXIe 5172 1_CH6_Site1 PXIe 5172 General Purpose Up to 100MHz HICC FAU...

Страница 11: ...172 2_CH3_Site1 PXIe 5172 2_CH5_Site1 PXIe 5172 2_CH7_Site1 DMM_Site1_4 DMM_Site1_5 AWG_CH2_to_SIte1 PXIe 5172 1_CH0_Site1 PXIe 5172 1_CH2_Site1 PXIe 5172 1_CH4_Site1 PXIe 5172 1_CH6_Site1 PXIe 5172 2...

Страница 12: ...C28 C36 4 1uF CAP CERM 1 uF 50 V 10 X7R 0805 0805 885012207103 Wurth Elektronik C22 C25 C29 C37 4 1000pF CAP CERM 1000 pF 50 V 10 X7R 0805 0805 C0805C102K5RACTU Kemet C30 1 100uF CAP Tantalum Polymer...

Страница 13: ...Ltd R31 1 135k RES 135 k 0 1 0 125 W 0805 0805 RT0805BRD07135KL Yageo America R33 1 191k RES 191 k 1 0 125 W AEC Q200 Grade 0 0805 0805 CRCW0805191KFKEA Vishay Dale R35 1 1 00Meg RES 1 00 M 0 5 0 1 W...

Страница 14: ...0 0805 0805 08055A102KAT2A AVX C12 0 0 01uF CAP CERM 0 01 uF 50 V 20 X7R 0805 0805 C0805C103M5RACTU Kemet C13 0 0 47uF CAP CERM 0 47 uF 50 V 10 X7R AEC Q200 Grade 1 0805 0805 GCM21BR71H474KA55L MuRata...

Страница 15: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Страница 16: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Страница 17: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Страница 18: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Страница 19: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Страница 20: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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