3 EVM Connectors and Test Points
TPS7H5001-SP Radiation-Hardness-Assured Si and GaN Dual Output Controller
✓
means that
the test point is included in the EVM.
Table 3-1. EVM Board Connections
Test Point
5001
5002
5003
5004
Connection
Description
TP1, J1
✓
✓
✓
✓
OUTA
Connected to the gate driver in the design.
Components R5, C5 can be used to test
different R/C loads.
TP2, J2
✓
✓
OUTB
Connected to the gate driver in the design.
Components R6, C6 can be used to test
different R/C loads.
TP3, J3
✓
✓
✓
SRA
Connected to the gate driver in the design.
Components R7, C7 can be used to test
different R/C loads.
TP4, J4
✓
SRB
Connected to the gate driver in the design.
Components R8, C8 can be used to test
different R/C loads.
TP5, TP6
✓
✓
✓
✓
CS_LIM
Input for current sense in the design.
The CS_LIM circuit provides small triangle
waveform from OUTA, OUTB. Note that
this can load OUTA, OUTB causing a
slow in the slew rate. If R9 and R10 are
unpopulated, CS_LIM can be force from
TP5.
TP7
✓
✓
✓
✓
VIN
Voltage input for the
TPS7H5001/2/3/4EVM-CVAL device
TP8
✓
✓
✓
✓
EN
Enable pin for the TPS7H5001/2/3/4EVM-
CVAL device, currently pulled high to VLDO
TP9
✓
✓
✓
✓
COMP
Error amplifier output for the
TPS7H5001/2/3/4EVM-CVAL, forcing this
voltage runs the TPS7H5001/2/3/4EVM-
CVAL in open loop.
TP10
✓
✓
✓
✓
REFCAP
Internal reference for
TPS7H5001/2/3/4EVM-CVAL
TP11, TP12
✓
✓
✓
✓
SS
In a closed loop design, this slowly
increases converter output voltage during
start-up
TP13, TP15
✓
✓
✓
✓
SYNC
Inputting a clock on this pin synchronizes
the TPS7H5001/2/3/4EVM-CVAL to a
frequency half of the input frequency
TP14
✓
✓
✓
✓
VLDO
Internal voltage rail for device logic
TP20
✓
✓
✓
✓
VSENSE
Voltage sense for the
TPS7H5001/2/3/4EVM-CVAL. Connected
to converter output voltage in the full
design.
TP21
✓
✓
✓
✓
RSC
Slope compensation selection resistor. Sets
slope compensation slew rate internal to
the device.
EVM Connectors and Test Points
SLVUCD0 – FEBRUARY 2022
TPS7H500x-SP Evaluation Module User's Guide
7
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