Texas Instruments TPS7H4010EVM, Руководство пользователя

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for simple PCB layout with optimal EMI and thermal performance. Protection features of the device include
thermal shutdown, input undervoltage lockout, cycle-by-cycle current limiting, and hiccup short-circuit protection.
The pin configuration of the TPS7H4010-SEP is shown in Figure 1-2 and the schematic is shown in Figure 1-3
for your quick reference.
VCC
RT
BIAS
SS/TRK
2
3
4 23
25
24
PVIN
SW
SW
DAP PVIN
PGND
SW
22
26
1
5
CBOOT
SW
PGND
21 6
PGND
PGND
20
7
PGOOD
19 8 AGND
9
10
18
17
EN
FB
SYNC/
MODE
16 11
29 28 27 30
13 14 15 12
SW PVIN
NC NC NC NC
NC NC NC NC
Figure 1-2. TPS7H4010-SEP Pin Configuration (30-
Pin WQFN Package Top View)
Copyright © 2017, Texas Instruments Incorporated
C
SS
R
T
R
SYNC
R
ENT
R
ENB
SW
PVIN
PGND
CBOOT
VCC
BIAS
EN
AGND
FB
V
IN
C
OUT
C
BOOT
C
IN
C
VCC
V
OUT
R
FBT
R
FBB
L
SYNC/
MODE
RT
SS/TRK
PGOOD
Figure 1-3. TPS7H4010-SEP Schematic
1.3 TPS7H4010-SEP Evaluation Module
The TPS7H4010-SEP evaluation module is orderable part number TPS7H4010EVM. The EVM contains two
independent converter circuits targeting two common applications:
• POLA: FSW=500 kHz, PVIN=5 V, VOUT=1.8 V, IOUT=0 A to 6 A
• POLB: FSW=500 kHz, PVIN=12 V, VOUT=3.3 V, IOUT=0 A to 6 A
Although the device operates over a wide PVIN range of 3.5 V to 30 V, the two circuits are optimized for PVIN of
5 V and 12 V.
Table 1-2 summarizes the two circuits.
Table 1-2. Converter Circuit Variants
Label U1/U2 I
OUT
Switching
Frequency
V
IN
Range V
OUT
POLA_VOUT_1.8V TPS7H4010-SEP 6 A 500 kHz 5 to 30 V 1.8 V
POLB_VOUT_3.3V TPS7H4010-SEP 6 A 500 kHz 5 to 30 V 3.3 V
It is worth noting that the package size of the TPS7H4010-SEP at U1 and U2 is not large enough to hold the full
device name. The devices are labeled 'PS7H4010' as shown in graphic below. Despite the device name starting
with "P", these devices are production devices and should not be mistaken for protoypes.
Introduction www.ti.com
4 TPS7H4010EVM User's Guide SNVU744 – OCTOBER 2020
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