Texas Instruments TPS7H4002EVM-CVAL, Руководство пользователя

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1 TPS7H4002EVM-CVAL Overview
The TPS7H4002-SP is a radiation hardened, 3-V to 5.5-V, 3-A synchronous step-down converter with integrated
high-side and low-side MOSFETs. High efficiency and efficient usage of space are achieved through low
resistance MOSFETs and a current mode control implementation.
The EVM is configured in a default state to accept a 5-V input but can be modified to disable or change the
undervoltage lock out (UVLO) protection, allowing for any input voltage from 3 V to 5.5 V. The EVM is also
configured for a 2.5-V output at a maximum peak output current of 3 A. Again, the regulated output voltage can
be modified by changing one resistor on the board. The TSP7H4002-SP has a dedicated soft start, enable, and
power good pins providing design flexibility to meet specific application requirements.
1.1 Features
• 0.807-V ±1.5% voltage reference overtemperature, radiation, and line and load regulation
• Adjustable soft start
• Adjustable input enable and undervoltage lockout (UVLO)
• Power good indicator pin
• Maximum output current of 3 A
1.2 Applications
• Point of load regulation
• Supports harsh environment applications
• Space satellite point of load supply for FPGAs, microcontrollers, data converters, and ASICs
• Space satellite payloads
• Radiation hardened applications
2 TPS7H4002EVM-CVAL Default Configuration
Table 2-1 describes the default configuration of the TPS7H4002EVM-CVAL listing the external components that
define the converter design.
Table 2-1. Default EVM Configuration
Parameter Specifications Description
Input power supply 5 V Bound by UVLO enable circuit (R13, R15)
Regulated output voltage 2.5 V R7 (RTOP) = 10 kΩ, R5 (RBOTTOM) = 4.7 kΩ
L
OUT
2.2 µH Chosen to meet inductor ripple current of 40% (Kind = 0.4)
C
OUT
330 µF
Chosen for (1) ESR = 6 mΩ to set output voltage ripple;
(2) value used during single event effects testing ensuring regulation maintained
with single event upset to switching
Output current 0 to 3 A By design
Switching frequency 500 kHz Set by R10 (RT) = 95.3 kΩ
Soft start time constant ≈ 3.2 ms Set by C1 (Css) = 10 nF
UVLO enable rising ≈ 4.432 V Set by R13 = 10 kΩ and R15 = 3.4 kΩ
UVLO enable falling ≈ 4.284 V Set by R13 = 10 kΩ and R15 = 3.4 kΩ
Loop bandwidth ≈ 30 kHz
Set by operational transconductance amplifier (OTA) compensation circuit: R14
(RCOMP) = 11.8 kΩ, C14 (CCOMP) = 22 nF, C6 (CHF) = 22 pF
Loop phase margin ≈ 60°
Gain margin ≈ –25 dB
www.ti.com TPS7H4002EVM-CVAL Overview
SLVUBI1 – MAY 2021
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