2.2 Optional Load Transient Input/Output Connector Descriptions
2.2.1 VDD and GND
VDD and GND are the connection terminals for the input supply of the load transient circuit. The VDD terminal is
the positive connection, and the GND terminal is the negative (that is, ground) connection.
2.2.2 J20
J20 is an optional connection for the user to make measurements or apply loads to the output of the LDO.
2.2.3 J22
J22 is an optional connection to insert a damping circuit across the load transient MOSFET drain to source
voltage.
2.2.4 J23
J23 is an optional connection to insert capacitance or additional load across the drain to source of the load
transient MOSFET.
2.2.5 J25
J25 is the connection for the function generator to drive the gate driver device. J25 is terminated by the 50-Ω
resistor, R24.
2.2.6 J26
J26 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET
drain to source voltage.
2.2.7 J28
J28 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET
gate to source voltage.
2.2.8 TP2
TP2 is the test point used to enable the gate driver device. Tie this pin to GND to enable the gate driver.
2.3 TPS7A74 LDO Operation and Component Selection
The TPS7A74EVM-068 evaluation module contains the TPS7A74 LDO with input, bias, soft-start, and output
capacitors installed, as well as feedback resistors installed. These seven components provide an implementation
example, as illustrated by the white boxes in
. The prepopulated capacitors are sized to ensure the
minimum capacitance requirements are maintained under all normal operating conditions. Optional pads are
available to test the LDO with additional setpoint options, as well as input, bias, and output capacitors beyond
what is already installed on the EVM.
Setpoint resistors are prepopulated on the TPS7A74EVM-068 to provide an output voltage of 1 V, 1.2 V, 1.5 V,
1.8 V, or 3.3 V. Select one of these output voltages by using the provided shunt to short the necessary pin on
header J16. If 0.65 V is desired on VOUT, remove the shunt from J16 and short J6. For other voltage options,
resistor R10 can be populated and R1 modified as necessary. See the
Application and Implementation
section in
the TPS7A74 data sheet for guidance on selecting R10 and R1 for alternate values of VOUT.
The TPS7A74 LDO can be enabled or disabled by using the J9 3-pin header:
• Place a 2-pin shunt across the header to tie VIN to EN to enable the device
• Place a 2-pin shunt across the header to tie GND to EN to disable the device
Alternatively, by connecting an external function generator to TP1 (EN) and a nearby GND post (J17), the
user can enable or disable the TPS7A74 LDO after VIN is applied.
TPS7A74EVM-068 during turn-on. The blue trace is the enable voltage, the green trace is the output voltage,
and the red trace is the load current.
Setup
4
TPS7A74EVM-068 Evaluation Module
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