Texas Instruments TPS7A53EVM-080, Руководство пользователя, Страница: 8 / 17

3 Board Layout
Figure 3-1 through Figure 3-8 illustrate the board layout for the TPS7A53EVM-080 PCB.
The TPS7A53EVM-080 dissipates power, which can cause some components to experience an increase in
temperature. The TPS7A53A-Q1 LDO and pulsed resistors R8, R9, R10, R11, and R12 are most at risk of
raising the junction temperature during normal operation. The LDO can become hot to the touch during normal
operation, see the thermal impedance discussion in the TPS7A53A-Q1 data sheet.
Figure 3-1. Top Assembly Layer and Silkscreen Figure 3-2. Top Layer Routing
Figure 3-3. Layer 2 Figure 3-4. Layer 3
Board Layout www.ti.com
8 TPS7A53EVM-080 Evaluation Module SBVU078 – NOVEMBER 2022
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