Connectors, Switches and Test Point Descriptions
4
Connectors, Switches and Test Point Descriptions
4.1
Power Connections
4.1.1
J1 – VIN
This header is the positive connection to the input power supply. The power supply must be connected
between J1 and J2 (GND). The leads to the input supply must be kept as short as possible. The input
voltage has to be between 5.4 V and 21 V.
4.1.2
J2 – GND
This header is the return connection to the input power supply for GND.
4.1.3
Output Voltage Rails
See
for header names, power source descriptions, and sequence.
Table 2. Output Rail Headers
Source
Header
Name
Turns On With
TPS650830EVM
TPS650831EVM
TPS650832EVM
J6
V3.3_DSW
VR3
POL, Discrete
VR3
Valid VIN
J7
V1.8A
VR2
VR5
VR2
Valid VIN
J10
V5A_DS3
VR5
POL, Discrete
VR5
SLP_SUS# Asserts Hign
POL, Load
J11
V3.3A_PCH
POL, Load Switch
POL, Load Switch
SLP_SUS# Asserts Hign
Switch
J14
V0.85A
VR1
VR2
POL, Discrete
SLP_SUS# Asserts Hign
J15
V1.00A
VR1
VR1
VR1
SLP_SUS# Asserts Hign
J16
VDDQ
VR4
VR4
VR4
SLP_S4# Asserts Hign
POL, Load
J19
V1.8U_2.5U
POL, Load Switch
POL, Load Switch
SLP_S4# Asserts Hign
Switch
POL, Load
J20
VCCIO
VR3
POL, Discrete
SLP_S3# Asserts Hign
Switch
J23
VTT
VLDO1
VLDO1
VLDO1
SLP_S0# Asserts Hign
4.2
Switches
4.2.1
S1 – PB_IN
This is the pushbutton input. Pressing S1 pulls PWRBTNIN to GND. The power button can be used for
many features such as turn on after a RESET or causing a RESET if configured correct via I2C. See the
datasheet for more options and uses of the power button.
4.2.2
S2 – Multi-Switch Shutdown, NVDC, and 3.3-V Load Switch
This switch has 4 dip switches in it. Switch 1 is unused. Switch 2 is internal 3.3-V load switch enable. Set
away from the ON position to enable the internal 3.3-V load switch. Switch 3 is NVDC selector. Set
towards the ON position to put the device into NVDC mode. Switch 4 is Shutdown mode. Set towards the
ON position to put the device into SHUTDOWN mode.
4.3
Enables
There are places for jumpers to enable the VRs directly on the board. However, the TPS650830EVM has
other jumpers that set the Sleep States for the device. The sleep states indirectly enable the VRs.
VR2 and VR3 are already on before any enable switch asserting high. They are enabled by DPWROK and
LDO3, respectively, with LDO3 enabled when VIN > UVLO.
10
TPS650830EVM-095
SLVUAD6 – December 2014
Copyright © 2014, Texas Instruments Incorporated